AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 352

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

27.4.10
27.5
352
I/O Lines Programming Example
AT91RM9200
Input Change Interrupt
The PIO Controller can be programmed to generate an interrupt when it detects an input change
on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable
Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the
input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask
Register). As Input change detection is possible only by comparing two successive samplings of
the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is
available, regardless of the configuration of the I/O line, i.e. configured as an input only, con-
trolled by the PIO Controller or assigned to a peripheral function.
When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt
Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt
line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to gen-
erate a single interrupt signal to the Advanced Interrupt Controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that
all the interrupts that are pending when PIO_ISR is read must be handled.
Figure 27-6. Input Change Interrupt Timings
The programing example shown in
configuration.
Table 27-1.
• 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain,
• Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no
• Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up
• Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input
• I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor
• I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor
• I/O lines 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor
Read PIO_ISR
with pull-up resistor
pull-up resistor
resistors, glitch filters and input change interrupts
change interrupt), no pull-up resistor, no glitch filter
PIO_PDSR
PIO_ISR
MCK
PIO_PER
PIO_PDR
Register
Programming Example
APB Access
Table 27-1
below is used to define the following
Value to be Written
0x0000 FFFF
0x0FFF 0000
APB Access
1768I–ATARM–09-Jul-09