AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 38

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

11.3.4.2
11.3.4.3
11.3.5
38
AT91RM9200
ARM Instruction Set Overview
Status Registers
Exception Types
A seventh processing mode, System Mode, does not have any banked registers. It uses the
User Mode registers. System Mode runs tasks that require a privileged processor mode and
allows them to invoke all classes of exceptions.
All other processor states are held in status registers. The current operating processor status is
in the Current Program Status Register (CPSR). The CPSR holds:
All five exception modes also have a Saved Program Status Register (SPSR) which holds the
CPSR of the task immediately before the exception occurred.
The
type. The types of exceptions are:
Exceptions are generated by internal and external sources.
More than one exception can occur at the same time.
When an exception occurs, the banked version of R14 and the SPSR for the exception mode
are used to save the state.
To return after handling the exception, the SPSR is moved to the CPSR and R14 is moved to the
PC. This can be done in two ways:
The ARM instruction set is divided into:
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition
code field (bits[31:28]).
For further details, see the ARM920T Technical Reference Manual, Rev. DDI0151C.
• four ALU flags (Negative, Zero, Carry, and Overflow),
• two interrupt disable bits (one for each type of interrupt),
• one bit to indicate ARM or Thumb execution
• five bits to encode the current processor mode
• fast interrupt (FIQ)
• normal interrupt (IRQ)
• memory aborts (used to implement memory protection or virtual memory)
• attempted execution of an undefined instruction
• software interrupt (SWIs)
• use of a data-processing instruction with the S-bit set, and the PC as the destination
• use of the Load Multiple with Restore CPSR instruction (LDM)
• Branch instructions
• Data processing instructions
• Status register transfer instructions
• Load and Store instructions
• Coprocessor instructions
• Exception-generating instructions
ARM9TDMI supports five types of exceptions and a privileged processing mode for each
1768I–ATARM–09-Jul-09