AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 162

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

18.6.3
18.6.3.1
18.6.3.2
Figure 18-11. Standard Read Protocol
18.6.3.3
162
AT91RM9200
Read Access
Read Protocols
Standard Read Protocol
Early Read Protocol
The SMC provides two alternative protocols for external memory read accesses: standard and
early read. The difference between the two protocols lies in the behavior of the NRD signal.
For write accesses, in both protocols, NWE has the same behavior. In the second half of the
master clock cycle, NWE always goes low (see
The protocol is selected by the DRP field in SMC_CSR
page
Note:
Standard read protocol implements a read cycle during which NRD and NWE are similar. Both
are active during the second half of the clock cycle. The first half of the clock cycle allows time to
ensure completion of the previous access as well as the output of address lines and NCS before
the read cycle begins.
During a standard read protocol, NCS is set low and address lines are valid at the beginning of
the external memory access, while NRD goes low only in the second half of the master clock
cycle to avoid bus conflict. See
Early read protocol provides more time for a read access from the memory by asserting NRD at
the beginning of the clock cycle. In the case of successive read cycles in the same memory,
NRD remains active continuously. Since a read cycle normally limits the speed of operation of
the external memory system, early read protocol can allow a faster clock frequency to be used.
However, an extra wait state is required in some cases to avoid contentions on the external bus.
190.). Standard read protocol is the default protocol after reset.
In the following waveforms and descriptions NWE represents NWE, NWR0 and NWR1 unless
NWR0 and NWR1 are otherwise represented. In addition, NCS represents NCS[7:0] (see
“I/O Lines” on page
D[15:0]
A[22:0]
MCK
NRD
NCS
157,
Table 18-1
Figure
18-11.
and
Table
Figure 18-18 on page
18-2).
(See “SMC Chip Select Registers” on
167).
1768I–ATARM–09-Jul-09
18.5.1