AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 425

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

30.6.3.8
1768I–ATARM–09-Jul-09
Receiver Time-out
Table 30-7.
The Receiver Time-out provides support in handling variable-length frames. This feature detects
an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel
Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an
end of frame.
The time-out delay period (during which the receiver waits for a new character) is programmed
in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at
0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR
remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO.
This counter is decremented at each bit period and reloaded each time a new character is
received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises.
The user can either:
If STTTO is performed, the counter clock is stopped until a first character is received. The idle
state on RXD before the start of the frame does not provide a time out. This prevents having to
obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is
detected.
If RETTO is performed, the counter starts counting down immediately from the value TO. This
enables generation of a periodic interrupt so that a user time-out can be handled, for example
when no key is pressed on a keyboard.
Figure 30-13
Figure 30-13. Receiver Time-out Block Diagram
• Obtain an interrupt when a time-out is detected after having received at least one character.
• Obtain a periodic interrupt while no character is received. This is performed by writing
RETTO
This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out)
bit at 1.
US_CR with the RETTO (Reload and Start Time-out) bit at 1.
Character
Received
Baud Rate
STTTO
115200
56000
57600
shows the block diagram of the Receiver Time out feature.
Maximum Timeguard Length Depending on Baud Rate (Continued)
1
D
Clear
Q
Baud Rate
Clock
Clock
Bit time
17.9
17.4
8.7
16-bit Time-out
Counter
TO
Load
16-bit
Value
AT91RM9200
0
Timeguard
4.55
4.43
2.21
=
TIMEOUT
425