AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 64

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

12.6.4.1
64
AT91RM9200
Trace Port
The Embedded Trace Macrocell of the AT91RM9200 works in half-rate clock mode and thus
integrates a clock divider. This assures that the maximum frequency of all the trace port signals
do not exceed one half of the ARM920T clock speed.
The Embedded Trace Macrocell input and output resources are not used in the AT91RM9200.
The Embedded Trace is a real-time trace module with the capability of tracing the ARM9TDMI
instruction and data.
The Embedded Trace debug features are only accessible in the AT91RM9200 BGA package.
For further details on Embedded Trace Macrocell, see the ETM9 (Rev2a) Technical Reference
Manual, ARM Ltd. -DDI 0157E.
The Trace Port is made up of the following pins:
The trace packet information (address, data) is associated with the processor state indicated by
TPS. Some processor states have no additional data associated with the Trace Packet Port (i.e.
failed condition code of an instruction). The packet is 8-bits wide, and up to two packets can be
output per cycle.
• Eight memory map decoder inputs
• Two counters
• One sequencer
• Four external inputs
• One external output
• One 18-byte FIFO
• TSYNC - the synchronization signal (Indicates the start of a branch sequence on the trace
• TCLK - the Trace Port clock, half-rate of the ARM920T processor clock.
• TPS0 to TPS2 - indicate the processor state at each trace clock edge.
• TPK0 to TPK15 - the Trace Packet data value.
packet port.)
1768I–ATARM–09-Jul-09