AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 33

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

11. ARM920T Processor Overview
11.1
1768I–ATARM–09-Jul-09
Overview
The ARM920T cached processor is a member of the ARM9
32-bit system-on-a-chip processors. It provides a complete high performance CPU subsystem
including:
The ARM9TDMI core within the ARM920T executes both the 32-bit ARM and 16-bit Thumb
instruction sets. The ARM9TDMI processor is a Harvard architecture device, implementing a
five-stage pipeline consisting of Fetch, Decode, Execute, Memory and Write stages.
The ARM920T processor incorporates two coprocessors:
The main features of the ARM920T processor are:
• ARM9TDMI RISC integer CPU
• 16-Kbyte instruction and 16-Kbyte data caches
• Instruction and data memory management units (MMUs)
• Write buffer
• AMBA
• Embedded Trace Macrocell (ETM) interface
• CP14 - Controls software access to the debug communication channel
• CP15 - System Control Processor, providing 16 additional registers that are used to configure
• ARM9TDMI-based, ARM Architecture v4T
• Two Instruction Sets
• 5-Stage Pipeline Architecture
• 16-Kbyte Data Cache, 16-Kbyte Instruction Cache
• Write Buffer
and control the caches, the MMU, protection system, clocking mode and other system
options
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory Access (M)
– Register Write (W)
– Virtually-addressed 64-way Associative Cache
– 8 Words per Line
– Write-though and Write-back Operation
– Pseudo-random or Round-robin Replacement
– Low-power CAM RAM Implementation
– 16-word Data Buffer
– 4-address Address Buffer
– Software Control Drain
™
(Advanced Microprocessor Bus Architecture) bus interface
™
Thumb family of high-performance
AT91RM9200
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