AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 264

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

23.4
23.4.1
23.4.2
23.4.3
264
Functional Description
AT91RM9200
Operating Modes Definition
Clock Definitions
Clock Generator
The following operating modes are supported by the PMC and offer different power consumption
levels and event response latency times:
The Power Management Controller provides the following clocks:
The Clock Generator embeds:
The Clock Generator may optionally integrate a divider by 2. The ARM7-based systems gener-
ally embed PLLs able to output between 20 MHz and 100 MHz and do not embed the divider
by 2. The ARM9-based systems generally embed PLLs able to output between 80 MHz and
180 MHz. As the 48 MHz required by the USB cannot be reached by such a PLL, the optional
divider by 2 is implemented.
The block diagram of the Clock Generator is shown in
• Normal Mode: The ARM processor clock is enabled and peripheral clocks are enabled
• Idle Mode: The ARM processor clock is disabled and waiting for the next interrupt (or a main
• Slow Clock Mode: Slow clock mode is similar to normal mode, but the main oscillator and the
• Standby Mode: Standby mode is a combination of Slow Clock mode and Idle Mode. It
• Slow Clock (SLCK), typically at 32.768 kHz, is the only permanent clock within the system.
• Master Clock (MCK), programmable from a few hundred Hz to the maximum operating
• Processor Clock (PCK), typically the Master Clock for ARM7-based systems and a faster
• Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI,
• UDP Clock (UDPCK), typically at 48 MHz, required by the USB Device Port operations.
• UHP Clock (UHPCK), typically at 48 MHz, required by the USB Host Port operations.
• Programmable Clock Outputs (PCK0 to PCK3) can be selected from the clocks provided by
• the Slow Clock Oscillator
• the Main Oscillator
• two PLL and divider blocks, A and B
depending on application requirements.
reset). The peripheral clocks are enabled depending on application requirements. PDC
transfers are still possible.
PLL are switched off to save power and the processor and the peripherals run in Slow Clock
mode. Note that slow clock mode is the mode selected after the reset.
enables the processor to respond quickly to a wake-up event by keeping power consumption
very low.
frequency of the device. It is available to the modules running permanently, such as the AIC
and the Memory Controller.
clock on ARM9-based systems, switched off when entering idle mode.
TWI, TC, MCI, etc.) and independently controllable. In order to reduce the number of clock
names in a product, the Peripheral Clocks are named MCK in the product datasheet.
the clock generator and driven on the PCK0 to PCK3 pins.
Figure
23-2.
1768I–ATARM–09-Jul-09