AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 63

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

12.6
12.6.1
12.6.2
12.6.3
12.6.4
1768I–ATARM–09-Jul-09
Functional Description
Test Mode Pins
Embedded In-Circuit Emulator
Debug Unit
Embedded Trace Macrocell
Two dedicated pins (TST1, TST0) are used to define the test mode of the device. The user must
make sure that these pins are both tied at low level to ensure normal operating conditions. Other
values associated to these pins are manufacturing test reserved.
The ARM9TDMI Embedded In-Circuit Emulator is supported via the ICE/JTAG port. It is con-
nected to a host computer via an ICE interface. Debug support is implemented using an
ARM9TDMI core embedded within the ARM920T. The internal state of the ARM920T is exam-
ined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline
of the core without using the external data bus. Therefore, when in debug state, a store-multiple
(STM) can be inserted into the instruction pipeline. This exports the contents of the ARM9TDMI
registers. This data can be serially shifted out without affecting the rest of the system.
There are six scan chains inside the ARM920T processor which support testing, debugging, and
programming of the Embedded ICE. The scan chains are controlled by the ICE/JTAG port.
Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly
between ICE and JTAG operations. A chip reset must be performed (NRST and NTRST) after
JTAGSEL is changed. The test reset input to the embedded ICE (NTRST) is provided separately
to facilitate debug of the boot program.
For further details on the Embedded In-Circuit-Emulator, see the ARM920T Technical Refer-
ence Manual, ARM Ltd, - DDI 0151C.
The Debug Unit provides a two-pin (DXRD and TXRD) UART that can be used for several
debug and trace purposes and offers an ideal means for in-situ programming solutions and
debug monitor communication. Moreover, the link with two Peripheral DMA Controller channels
provides packet handling of these tasks with processor time reduced to a minimum.
The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals
that come from the ICE and trace the activity of the Debug Communication Channel.
The Debug Unit can be used to upload an application into internal SRAM. It is activated by the
boot program when no valid application is detected.
A specific register, the Debug Unit Chip ID Register, informs about the product version and its
internal configuration.
The AT91RM9200 Debug Unit Chip ID value is: 0x09290781, on 32-bit width.
For further details on the Debug Unit, see
For further details on the Debug Unit and the Boot program, see
The AT91RM9200 features an Embedded Trace Macrocell (ETM), which is closely connected to
the ARM9TDMI Processor. The Embedded Trace is a standard mid-level implementation and
contains the following resources:
• Four pairs of address comparators
• Two data comparators
“Debug Unit (DBGU)” on page
“Boot Program” on page
AT91RM9200
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