AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 609

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

1768I–ATARM–09-Jul-09
consists of two words. The first word is the address of the received buffer; the second is the
receive status.
To receive frames, the buffer queue must be initialized by writing an appropriate address to bits
[31:2] in the first word of each list entry. Bit zero of word zero must be written with zero.
After a frame is received, bit zero becomes set and the second word indicates what caused the
frame to be copied to memory. The start location of the received buffer descriptor list should be
written to the received buffer queue pointer register before receive is enabled (by setting the
receive enable bit in the network control register). As soon as the received block starts writing
received frame data to the receive FIFO, the received buffer manager reads the first receive buf-
fer location pointed to by the received buffer queue pointer register. If the filter block is active,
the frame should be copied to memory; the receive data DMA operation starts writing data into
the receive buffer. If an error occurs, the buffer is recovered. If the frame is received without
error, the queue entry is updated. The buffer pointer is rewritten to memory with its low-order bit
set to indicate successful frame reception and a used buffer. The next word is written with the
length of the frame and how the destination address was recognized. The next receive buffer
location is then read from the following word or, if the current buffer pointer had its wrap bit set,
the beginning of the table. The maximum number of buffer pointers before a wrap bit is seen is
1024. If a wrap bit is not seen by then, a wrap bit is assumed in that entry. The received buffer
queue pointer register must be written with zero in its lower-order bit positions to enable the
wrap function to work correctly.
If bit zero is set when the receive buffer manager reads the location of the receive buffer, then
the buffer has already been used and cannot be used again until software has processed the
frame and cleared bit zero. In this case, the DMA block sets the buffer unavailable bit in the
received status register and triggers an interrupt. The frame is discarded and the queue entry is
reread on reception of the next frame to see if the buffer is now available. Each discarded frame
increments a statistics register that is cleared on being read. When there is network congestion,
it is possible for the MAC to be programmed to apply back pressure.
This is when half-duplex mode collisions are forced on all received frames by transmitting 64 bits
of data (a default pattern).
Reading the received buffer queue register returns the location of the queue entry currently
being accessed. The queue wraps around to the start after either 1024 entries (i.e., 2048 words)
or when the wrap bit is found to be set in bit 1 of the first word of an entry.
Table 36-4.
Bit
Word 0
31:2
1
0
Word 1
31
Received Buffer Descriptor List
Table 36-4
Function
Base address of receive buffer
Wrap bit. If this bit is set, the counter that is ORed with the received buffer queue
pointer register to give the pointer to entries in this table is cleared after the buffer is
used.
Ownership bit. 1 indicates software owns the pointer, 0 indicates that the DMA owns
the buffer. If this bit is not zero when the entry is read by the receiver, the buffer
unavailable bit is set in the received status register and the receiver goes inactive.
Global all ones broadcast address detected
defines an entry in the received buffer descriptor list.
AT91RM9200
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