AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 199

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

19.6
19.6.1
Figure 19-3. Write Burst, 32-bit SDRAM Access
1768I–ATARM–09-Jul-09
D[31:0]
A[12:0]
SDWE
SDCS
SDCK
RAS
CAS
Functional Description
SDRAM Controller Write Cycle
Row n
The SDRAM Controller allows burst access or single access. To initiate a burst access, the
SDRAM Controller uses the transfer type signal provided by the master requesting the access. If
the next access is a sequential write access, writing to the SDRAM device is carried out. If the
next access is a write-sequential access, but the current access is to a boundary page, or if the
next access is in another row, then the SDRAM Controller generates a precharge command,
activates the new row and initiates a write command. To comply with SDRAM timing parame-
ters, additional clock cycles are inserted between precharge/active (t
active/write (t
19.7.3 “SDRAMC Configuration Register” on page
t
RCD
= 3
col a
Dna
RCD
) commands. For definition of these timing parameters, refer to the
col b
Dnb
col c
Dnc
col d
Dnd
col e
Dne
col f
Dnf
208. This is described in
col g
Dng
col h
Dnh
col i
Dni
AT91RM9200
col j
Dnj
RP
Figure 19-3
) commands and
col k
Dnk
col l
Dnl
Section
below.
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