AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 570

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

34.5.3.1
34.5.3.2
34.5.3.3
34.5.3.4
34.5.3.5
34.5.3.6
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AT91RM9200
From Powered State to Default State
From Default State to Address State
From Address State to Configured State
Enabling Suspend
Receiving a Host Resume
Sending an External Resume
After its connection to a USB host, the USB device waits for an end-of-bus reset. The USB host
stops driving a reset state once it has detected the device’s pull-up on DP. The unmasked flag
ENDBUSRES is set in the register UDP_ISR and an interrupt is triggered. The UDP software
enables the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, option-
ally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration
then begins by a control transfer.
After a set address standard device request, the USB host peripheral enters the address state.
Before this, it achieves the Status IN transaction of the control transfer, i.e., the UDP device sets
its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and
cleared.
To move to address state, the driver software sets the FADDEN flag in the UDP_GLB_STATE,
sets its new address, and sets the FEN bit in the UDP_FADDR register.
Once a valid Set Configuration standard request has been received and acknowledged, the
device enables endpoints corresponding to the current configuration. This is done by setting the
EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding
interrupts in the UDP_IER register.
When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the
UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR
register.
This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode.
As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator,
and goes into Idle Mode. It may also switch off other devices on the board.
The USB device peripheral clocks may be switched off. However, the transceiver and the USB
peripheral must not be switched off, otherwise the resume is not detected.
In suspend mode, the USB transceiver and the USB peripheral must be powered to detect the
RESUME. However, the USB device peripheral may not be clocked as the WAKEUP signal is
asynchronous.
Once the resume is detected on the bus, the signal WAKEUP in the UDP_ISR is set. It may gen-
erate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be
used to wake-up the core, enable PLL and main oscillators and configure clocks. The WAKEUP
bit must be cleared as soon as possible by setting WAKEUP in the UDP_ICR register.
The External Resume is negotiated with the host and enabled by setting the ESR bit in the
UDP_GLB_STATE. An asynchronous event on the ext_resume_pin of the peripheral generates
a WAKEUP interrupt. On early versions of the USP peripheral, the K-state on the USB line is
generated immediately. This means that the USB device must be able to answer to the host very
quickly. On recent versions, the software sets the RMWUPE bit in the UDP_GLB_STATE regis-
ter once it is ready to communicate with the host. The K-state on the bus is then generated.
1768I–ATARM–09-Jul-09