AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 598

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

35.4
35.4.1
598
Functional Description
AT91RM9200
Host Controller Interface
Please refer to the Open Host Controller Interface Specification for USB Release 1.0.a.
There are two communication channels between the Host Controller and the Host Controller
Driver. The first channel uses a set of operational registers located on the USB Host Controller.
The Host Controller is the target for all communications on this channel. The operational regis-
ters contain control, status and list pointer registers. They are mapped in the ASB memory
mapped area. Within the operational register set there is a pointer to a location in the processor
address space named the Host Controller Communication Area (HCCA). The HCCA is the sec-
ond communication channel. The host controller is the master for all communication on this
channel. The HCCA contains the head pointers to the interrupt Endpoint Descriptor lists, the
head pointer to the done queue and status information associated with start-of-frame
processing.
The basic building blocks for communication across the interface are Endpoint Descriptors (ED,
4 double words) and Transfer Descriptors (TD, 4 or 8 double words). The host controller assigns
an Endpoint Descriptor to each endpoint in the system. A queue of Transfer Descriptors is linked
to the Endpoint Descriptor for the specific endpoint.
Figure 35-2. USB Host Communication Channels
Device Enumeration
Open HCI
= Transfer Descriptor
Device Register
in Memory Space
Operational
Registers
Mode
HCCA
Status
Event
Frame Int
Ratio
Control
Bulk
Shared RAM
Host Controller
Communications Area
Interrupt 31
Interrupt 0
Interrupt 1
Interrupt 2
Done
. . .
. . .
. . .
= Endpoint Descriptor
1768I–ATARM–09-Jul-09