AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 228
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
AT91RM9200-CI-002
Manufacturer Part Number
AT91RM9200-CI-002
Description
IC ARM9 MCU 256 BGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91RM9200-EK.pdf
(41 pages)
2.AT91RM9200-DK.pdf
(2 pages)
3.AT91RM9200-QU-002.pdf
(701 pages)
Specifications of AT91RM9200-CI-002
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
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Manufacturer
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Price
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• PAGES: Page Size
This field defines the page size handling and the page size.
• OEL: Output Enable Latency
This field defines the number of idle cycles inserted after each level change on the BFOE output enable signal. OEL range
is 1 to 3.
• BAAEN: Burst Address Advance Enable
0: The burst clock is enabled to increment the burst address or, disabled to remain at the same address.
1: The burst clock is continuous and the burst address advance is controlled with the BFBAA pin.
• BFOEH: Burst Flash Output Enable Handling
0: No burst resume in Burst Mode. When the BFC is deselected, this causes an irreversible break of the burst. A new burst
will be initiated for the next access.
1: Burst resume. When the BFC is deselected, the burst is suspended. It will be resumed if the next access is sequential to
the last one.
• MUXEN: Multiplexed Bus Enable
0: The address and data busses operate independently.
1: The address and data busses are multiplexed. Actually, the address is presented on both the data bus and the address
bus when the BFAVD signal is asserted.
• RDYEN: Ready Enable Mode
0: The BFRDY input signal at the BFC input interface is ignored.
1: The BFRDY input signal is used as an indicator of data availability in the next cycle.
228
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AT91RM9200
Pages
0
0
1
1
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Page Size
No page handling. The Ready Signal (BFRDY) is sampled to check if the next
data is available.
16 bytes page size
32 bytes page size
64 bytes page size
128 bytes page size
256 bytes page size
512 bytes page size
1024 bytes page size
1768I–ATARM–09-Jul-09
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