AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 121

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

16. Memory Controller(MC)
16.1
1768I–ATARM–09-Jul-09
Overview
The Memory Controller (MC) manages the ASB bus and controls access by up to four masters.
It features a bus arbiter and an address decoder that splits the 4G bytes of address space into
areas to access the embedded SRAM and ROM, the embedded peripherals and the external
memories through the External Bus Interface (EBI). It also features an abort status and a mis-
alignment detector to assist in application debug.
The Memory Controller allows booting from the embedded ROM or from an external non-volatile
memory connected to the Chip Select 0 of the EBI. The Remap command switches addressing
of the ARM vectors (0x0 - 0x20) on the embedded SRAM.
Key Features of the AT91RM9200 Memory Controller are:
• Programmable Bus Arbiter Handling Four Masters
• Address Decoder Provides Selection For
• Boot Mode Select Option
• Abort Status Registers
• Misalignment Detector
• Remap Command
– Internal Bus is Shared by ARM920T, PDC, USB Host Port and Ethernet MAC
– Each Master Can Be Assigned a Priority Between 0 and 7
– Eight External 256-Mbyte Memory Areas
– Four Internal 1-Mbyte Memory Areas
– One 256-Mbyte Embedded Peripheral Area
– Non-volatile Boot Memory Can Be Internal or External
– Selection is Made By BMS Pin Sampled at Reset
– Source, Type and All Parameters of the Access Leading to an Abort are Saved
– Alignment Checking of All Data Accesses
– Abort Generation in Case of Misalignment
– Provides Remapping of an Internal SRAM in Place of the Boot NVM
Masters
AT91RM9200
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