AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 168

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

18.6.5
18.6.5.1
Figure 18-19. Read Access with Setup and Hold
Figure 18-20. Read Access with Setup
168
A[22:0]
MCK
NRD
AT91RM9200
Setup and Hold Cycles
Read Access
A[22:0]
MCK
NRD
The SMC allows some memory devices to be interfaced with different setup, hold and pulse
delays. These parameters are programmable and define the timing of each portion of the read
and write cycles. However, it is not possible to use this feature in early read protocol.
If an attempt is made to program the setup parameter as not equal to zero and the hold parame-
ter as equal to zero with WSEN = 0 (0 standard wait state), the SMC does not operate correctly.
If consecutive accesses are made to two different external memories and the second memory is
programmed with setup cycles, then no chip select change wait state is inserted (see
23 on page
When a data float wait state (t
memory bank is programmed with setup cycles, the SMC behaves as follows:
The read cycle can be divided into a setup, a pulse length and a hold. The setup parameter can
have a value between 1.5 and 7.5 clock cycles, the hold parameter between 0 and 7 clock
cycles and the pulse length between 1.5 and 128.5 clock cycles, by increments of one.
• If the number of t
• If the number of the setup cycle is higher than the number of t
NRD Setup
cycles inserted is equal to 0 (see
0 (see
Figure 18-25 on page
170).
NRD Setup
DF
is higher or equal to the number of setup cycles, the number of setup
DF
) is programmed on the first memory bank and when the second
171).
Figure 18-24 on page
Pulse Length
Pulse Length
170).
DF,
the number of t
NRD Hold
1768I–ATARM–09-Jul-09
DF
inserted is
Figure 18-