AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 270

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

23.4.7
23.4.7.1
270
AT91RM9200
Clock Controllers
Master Clock Controller
The Power Management Controller provides the clocks to the different peripherals of the sys-
tem, either internal or external. It embeds the following elements:
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is
the clock provided to all the peripherals and the memory controller.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting
the Slow Clock enables Slow Clock Mode by providing a 32.768 kHz signal to the whole device.
Selecting the Main Clock saves power consumption of both PLLs, but prevents using the USB
ports. Selecting the PLLB Clock saves the power consumption of the PLLA by running the pro-
cessor and the peripheral at 48 MHz required by the USB ports. Selecting the PLLA Clock runs
the processor and the peripherals at their maximum speed while running the USB ports at 48
MHz.
The Master Clock Controller is made up of a clock selector and a prescaler, as shown in
23-8. It also contains an optional Master Clock divider in products integrating an ARM9 proces-
sor. This allows the processor clock to be faster than the Master Clock.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in
PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the
selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler.
When the Master Clock divider is implemented, it can be programmed between 1 and 4 through
the MDIV field in PMC_MCKR.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in
PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can
trigger an interrupt to the processor. This feature is useful when switching from a high-speed
clock to a lower one to inform the software when the change is actually done.
Note:
• the Master Clock Controller, which selects the Master Clock.
• the Processor Clock Controller, which implements the Idle Mode.
• the Peripheral Clock Controller, which provides power saving by controlling clocks of the
• the USB Clock Controller, which distributes the 48 MHz clock to the USB controllers.
• the Programmable Clock Controller, which allows generation of up to four programmable
embedded peripherals.
clock signals on external pins.
A new value to be written in PMC_MCKR must not be the same as the current value in
PMC_MCKR.
1768I–ATARM–09-Jul-09
Figure