AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 605

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

36.5.1
36.5.1.1
36.5.1.2
36.5.2
1768I–ATARM–09-Jul-09
Media Independent Interface
Transmit/Receive Operation
General
RMII Transmit and Receive Operation
The Ethernet MAC is capable of interfacing to both RMII and MII Interfaces. The RMII bit in the
ETH_CFG register controls the interface that is selected. When this bit is set, the RMII interface
is selected, else the MII interface is selected.
The MII and RMII interface are capable of both 10Mb/s and 100Mb/s data rates as described in
the IEEE 802.3u standard. The signals used by the MII and RMII interfaces are described in the
Table
Table 36-1.
The intent of the RMII is to provide a reduced pin count alternative to the IEEE 802.3u MII. It
uses 2 bits for transmit (ETX0 and ETX1) and two bits for receive (ERX0 and ERX1). There is a
Transmit Enable (ETXEN), a Receive Error (ERXER), a Carrier Sense (ECRS_DV), and a 50
MHz Reference Clock (ETXCK_REFCK) for 100Mb/s data rate.
The same signals are used internally for both the RMII and the MII operations. The RMII maps
these signals in a more pin-efficient manner. The transmit and receive bits are converted from a
4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. The carrier sense
and data valid signals are combined into the ECRS_ECRSDV signal. This signal contains infor-
mation on carrier sense, FIFO status, and validity of the data. Transmit error bit (ETXER) and
collision detect (ECOL) are not used in RMII mode.
A standard IEEE 802.3 packet consists of the following fields: preamble, start of frame delimiter
(SFD), destination address (DA), source address (SA), length, data (Logical Link Control Data)
and frame check sequence CRC32 (FCS).
Table 36-2.
Pin Name
ETXCK_REFCK
ECRS_ECRSDV
ECOL
ERXDV
ERX0 - ERX3
ERXER
ERXCK
ETXEN
ETX0-ETX3
ETXER
Alternating 1s/0s
Up to 7 bytes
36-1.
Preamble
Pin Configurations
Packet Format
MII
ETXCK: Transmit Clock
ECRS: Carrier Sense
ECOL: Collision Detect
ERXDV: Data Valid
ERX0 - ERX3: 4-bit Receive Data
ERXER: Receive Error
ERXCK: Receive Clock
ETXEN: Transmit Enable
ETX0 - ETX3: 4-bit Transmit Data
ETXER: Transmit Error
1 byte
SFD
6 bytes
DA
6 bytes
SA
Length/type
2 bytes
RMII
REFCK: Reference Clock
ECRSDV: Carrier Sense/Data Valid
ERX0 - ERX1: 2-bit Receive Data
ERXER: Receive Error
ETXEN: Transmit Enable
ETX0 - ETX1: 2-bit Transmit Data
Frame
(1)
LLC Data
AT91RM9200
PAD
4 bytes
FCS
605