AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 221

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Figure 20-5. Asynchronous Read and Write Accesses with Non-multiplexed Address and Data
20.6.4
20.6.4.1
20.6.4.2
1768I–ATARM–09-Jul-09
BFAVD
D[15:0]
D[15:0]
Burst Flash Controller Synchronous Mode
A[24:0]
Output
BFWE
BFOE
BFCS
BFCK
Input
Burst Read Protocols
Read Access in Burst Mode
Writing the Burst Flash Controller Operating Mode field (BFCOM) to 2
ler Mode Register” on page 227.
BFCK pin. Only read accesses are treated and write accesses are ignored. The BFC supports
read access of bytes, half-words or words.
The BFC supports two burst read protocols:
When a read access is requested in Burst Mode, the requested address is registered in the
BFC. For subsequent read accesses, the address is compared to the previous one. Then the
two following cases are considered:
• Clock Controlled Address Advance, the internal address of the burst Flash is automatically
• Signal Controlled Address Advance, the internal address of the burst Flash is incremented
1. In case of a non-sequential access, the current burst is broken and the BFC launches a
incremented at each BFCK cycle.
only when the BFBAA signal is active.
new burst by performing an address latch cycle. The address is presented on the
address bus in any case and on the data bus if the multiplexed bus option is enabled.
Asynchronous
Read Access
Read Address
AVL
Address Valid Latency = 4 BFCK cycles (AVL field = 3)
Output Enable Latency (OEL) = 1 BFCK cycle
Data
OEL = 1
puts the BFC in Burst Mode. The BFC Clock is driven on the
Asynchronous
Write Access
Write Address
AVL
Data
See “Burst Flash Control-
AT91RM9200
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