AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 272

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

23.4.7.4
23.4.7.5
272
USB Device Clock Control
USB Device Port Suspend
USB Host Clock Control
AT91RM9200
USB Clock Controller
Programmable Clock Output Controller
If using one of the USB ports, the user has to program the Divider and PLL B block to output a
48 MHz signal with an accuracy of ± 0.25%.
When the clock for the USB is stable, the USB device and host clocks, UDPCK and UHPCK, can
be enabled. They can be disabled when the USB transactions are finished, so that the power
consumption generated by the 48 MHz signal on these peripherals is saved.
The USB ports require both the 48 MHz signal and the Master Clock. The Master Clock may be
controlled via the Peripheral Clock Controller.
The USB Device Port clock UDPCK can be enabled by writing 1 at the UDP bit in PMC_SCER
(System Clock Enable Register) and disabled by writing 1 at the bit UDP in PMC_SCDR (Sys-
tem Clock Disable Register). The activity of UDPCK is shown in the bit UDP of PMC_SCSR
(System Clock Status Register).
When the USB Device Port detects a suspend condition, the 48 MHz clock is automatically dis-
abled, i.e., the UDP bit in PMC_SCSR is cleared. It is also possible to automatically disable the
Master Clock provided to the USB Device Port on a suspend condition. The MCKUDP bit in
PMC_SCSR configures this feature and can be set or cleared by writing one in the same bit of
PMC_SCER and PMC_SCDR.
The USB Host Port clock UHPCK can be enabled by writing 1 at the UHP bit in PMC_SCER
(System Clock Enable Register) and disabled by writing 1 at the UHP bit in PMC_SCDR (Sys-
tem Clock Disable Register). The activity of UDPCK is shown in the bit UHP of PMC_SCSR
(System Clock Status Register).
The PMC controls up to four signals to be output on external pins PCK0 to PCK3. Each signal
can be independently programmed via the registers PMC_PCK0 to PMC_PCK3.
PCK0 to PCK3 can be independently selected between the four clocks provided by the Clock
Generator by writing the CSS field in PMC_PCK0 to PMC_PCK3. Each output signal can also
be divided by a power of 2 between 1 and 64 by writing the field PRES (Prescaler) in
PMC_PCK0 to PMC_PCK3.
Each output signal can be enabled and disabled by writing 1 in the corresponding bit PCK0 to
PCK3 of PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output
clocks are given in the bits PCK0 to PCK3 of PMC_SCSR (System Clock Status Register).
Moreover, like the MCK, a status bit in PMC_SR indicates that the Programmable Clock is actu-
ally what has been programmed in the Programmable Clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching
clocks, it is strongly recommended to disable the Programmable Clock before any configuration
change and to re-enable it after the change is actually performed.
Note also that it is required to assign the pin to the Programmable Clock operation in the PIO
Controller to enable the signal to be driven on the pin.
1768I–ATARM–09-Jul-09