AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 420

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

30.6.3.2
420
AT91RM9200
Asynchronous Receiver
Figure 30-6. Transmitter Status
If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver over-
samples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock,
depending on the OVER bit in the Mode Register (US_MR).
The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start
bit is detected and data, parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data
bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8
(OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop
bit are sampled on each 8 sampling clock cycle.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits
as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. The number of stop bits
has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP,
so that resynchronization between the receiver and the transmitter can occur. Moreover, as
soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchroni-
zation can also be accomplished when the transmitter is operating with one stop bit.
Figure 30-7
operates in asynchronous mode.
Baud Rate
TXEMPTY
US_THR
TXRDY
Clock
Write
TXD
and
Start
Figure 30-8
Bit
D0
D1
D2
illustrate start detection and character reception when USART
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
Start
Bit
D0
D1
D2
D3
D4
D5
D6
1768I–ATARM–09-Jul-09
D7
Parity
Bit
Stop
Bit