AT91RM9200-CI-002 Atmel, AT91RM9200-CI-002 Datasheet - Page 629

• Manufacturer Part Number: AT91RM9200-CI-002
• Description: IC ARM9 MCU 256 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-CI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

36.6.18
These registers reset to zero on a read and remain at all ones when they count to their maximum value. They should be
read frequently enough to prevent loss of data.
The statistics register block contains the registers found in
Table 36-6.
1768I–ATARM–09-Jul-09
Register
Frames Transmitted OK Register
Single Collision Frame Register
Multiple Collision Frame
Register
Frames Received OK Register
Frame Check Sequence Error
Register
Alignment Error Register
Deferred Transmission Frame
Register
Late Collision Register
Excessive Collision Register
Transmit Underrun Error
Register
Carrier Sense Error Register
Discard RX Frame Register
Receive Overrun Register
Code Error Register
EMAC Statistics Register Block Registers
EMAC Statistic Register Block Register Descriptions
Register Name
ETH_FRA
ETH_SCOL
ETH_MCOL
ETH_OK
ETH_SEQE
ETH_ALE
ETH_DTE
ETH_LCOL
ETH_ECOL
ETH_TUE
ETH_CSE
ETH_DRFC
ETH_ROV
ETH_CDE
Description
before being transmitted and experiencing no carrier loss nor underrun.
A 16-bit register counting the number of frames experiencing between two and
fifteen collisions prior to being transmitted (62 - 1518 bytes, no carrier loss, no
underrun).
A 24-bit register counting the number of good frames received, i.e., address
recognized. A good frame is of length 64 to 1518 bytes and has no FCS,
alignment or code errors.
An 8-bit register counting address-recognized frames that are an integral
number of bytes long, that have bad CRC and that are 64 to 1518 bytes long.
An 8-bit register counting frames that:
- are address-recognized,
- are not an integral number of bytes long,
- have bad CRC when their length is truncated to an integral number of bytes,
- are between 64 and 1518 bytes long.
A 16-bit register counting the number of frames experiencing deferral due to
carrier sense active on their first attempt at transmission (no underrun or
collision).
An 8-bit register counting the number of frames that experience a collision after
the slot time (512 bits) has expired. No carrier loss or underrun. A late collision
is counted twice, i.e., both as a collision and a late collision.
An 8-bit register counting the number of frames that failed to be transmitted
because they experienced 16 collisions (64 - 1518 bytes, no carrier loss or
underrun).
An 8-bit register counting the number of frames not transmitted due to a
transmit DMA underrun. If this register is incremented, then no other register is
incremented.
An 8-bit register counting the number of frames for which carrier sense was not
detected and that were maintained in half-duplex mode one slot time (512 bits)
after the start of transmission (no excessive collision).
This 16-bit counter is incremented every time an address-recognized frame is
received but cannot be copied to memory because no receive buffer is
available.
An 8-bit register counting the number of frames that are address-recognized
but were not copied to memory due to a receive DMA overrun.
An 8-bit register counting the number of frames that are address-recognized,
had RXER asserted during reception. If this counter is incremented, then no
other counters are incremented.
A 24-bit register counting the number of frames successfully transmitted.
A 16-bit register counting the number of frames experiencing a single collision
Table
36-6.
AT91RM9200
629