ATMEGA128-16AI Atmel, ATMEGA128-16AI Datasheet - Page 264

• Manufacturer Part Number: ATMEGA128-16AI
• Description: IC AVR MCU 128K 16MHZ 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q1167170A

264
ATmega128
The Atmel
approximation algorithm implemented in the digital logic. When used in Boundary-scan, the
problem is usually to ensure that an applied analog voltage is measured within some limits. This
can easily be done without running a successive approximation algorithm: apply the lower limit
on the digital DAC[9:0] lines, make sure the output from the comparator is low, then apply the
upper limit on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following
•
•
•
As an example, consider the task of verifying a 1.5V ±5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
The recommended values from
rithm in
“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
Table 105. Algorithm for Using the ADC
Step
1
2
3
4
5
6
7
8
The Port Pin for the ADC channel in use must be configured to be an input with pull-up
disabled to avoid signal contention.
In normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal
low (Sample mode).
Table
Actions
SAMPLE_
PRELOAD
EXTEST
Verify the
COMP bit
scanned
out to be 0
®
AVR
105. Only the DAC and Port Pin values of the Scan Chain are shown. The column
®
The lower limit is:
The upper limit is:
ADC is based on the analog circuitry shown in
ADCEN
1
1
1
1
1
1
1
1
DAC
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
Table 104
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
1024 1.5V 0,95 5V
1024 1.5V 1.05 5V
⋅
⋅
are used unless other values are given in the algo-
HOLD
1
0
1
1
1
1
0
1
⋅
⋅
⁄
⁄
PRECH
1
1
1
1
0
1
1
1
=
=
291
323
PA3.
Data
0
0
0
0
0
0
0
0
CC
=
=
Figure 131
.
0x123
0x143
PA3.
Control
0
0
0
0
0
0
0
0
with a successive
PA3.
Pullup_
Enable
0
0
0
0
0
0
0
0
2467V–AVR–02/11