ATMEGA128-16AI Atmel, ATMEGA128-16AI Datasheet - Page 300

IC AVR MCU 128K 16MHZ 64-TQFP

ATMEGA128-16AI

Manufacturer Part Number
ATMEGA128-16AI
Description
IC AVR MCU 128K 16MHZ 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128-16AI

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Q1167170A

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Serial
Downloading
SPI Serial
Programming Pin
Mapping
300
ATmega128
Table 126. Parallel Programming Characteristics, V
Notes:
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface. Note that throughout the description about Serial downloading, MOSI and MISO
are used to describe the serial data in and serial data out respectively. For Atmel
AVR
Even though the SPI Programming interface re-uses the SPI I/O module, there is one important
difference: The MOSI/MISO pins that are mapped to PB2 and PB3 in the SPI I/O module are not
used in the Programming interface. Instead, PE0 and PE1 are used for data in SPI Program-
ming mode as shown in
Table 127. Pin Mapping SPI Serial Programming
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
XLPH
PLXH
BVPH
PHPL
PLBX
WLBX
PLWL
BVWL
WLWH
WLRL
WLRH
WLRH_CE
XLOL
BVDV
OLDV
OHDZ
®
ATmega128 these pins are mapped to PDI and PDO.
1.
2. t
MISO (PDO)
MOSI (PDI)
Symbol
commands.
t
WLRH_CE
SCK
WLRH
Parameter
XTAL1 Low to PAGEL high
PAGEL low to XTAL1 high
BS1 Valid before PAGEL High
PAGEL Pulse Width High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR Low
PAGEL Low to WR Low
BS1 Valid to WR Low
WR Pulse Width Low
WR Low to RDY/BSY Low
WR Low to RDY/BSY High
WR Low to RDY/BSY High for Chip Erase
XTAL1 Low to OE Low
BS1 Valid to DATA valid
OE Low to DATA Valid
OE High to DATA Tri-stated
is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
is valid for the Chip Erase command.
Table
127.
Pins
PE0
PE1
PB1
(1)
I/O
O
I
I
(2)
CC
= 5 V ±10% (Continued)
Min
150
150
150
3.7
7.5
67
67
67
67
67
0
0
0
0
Table 127 on page
Serial data out
Serial data in
Description
Serial clock
Typ
Max
250
250
250
10
1
5
Units
ms
ms
2467V–AVR–02/11
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
300, the pin
®

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