ATMEGA128-16AI Atmel, ATMEGA128-16AI Datasheet - Page 213

• Manufacturer Part Number: ATMEGA128-16AI
• Description: IC AVR MCU 128K 16MHZ 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q1167170A

2467V–AVR–02/11
Figure 96. Data Transfer in Master Transmitter Mode
A START condition is sent by writing the following value to TWCR:
TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to
transmit a START condition and TWINT must be written to one to clear the TWINT flag. The TWI
will then test the Two-wire Serial Bus and generate a START condition as soon as the bus
becomes free. After a START condition has been transmitted, the TWINT flag is set by hard-
ware, and the status code in TWSR will be $08 (See
SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit
should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing
the following value to TWCR:
When SLA+W have been transmitted and an acknowledgment bit has been received, TWINT is
set again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are $18, $20, or $38. The appropriate action to be taken for each of these status codes is
detailed in
When SLA+W has been successfully transmitted, a data packet should be transmitted. This is
done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not,
the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Regis-
ter. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the
transfer. This is accomplished by writing the following value to TWCR:
This scheme is repeated until the last byte has been sent and the transfer is ended by generat-
ing a STOP condition or a repeated START condition. A STOP condition is generated by writing
the following value to TWCR:
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR
value
TWCR
value
TWCR
value
TWCR
value
TWCR
value
SDA
SCL
Table
TWINT
TWINT
TWINT
TWINT
TWINT
1
1
1
1
1
88.
TRANSMITTER
Device 1
MASTER
TWEA
TWEA
TWEA
TWEA
TWEA
X
X
X
X
X
Device 2
RECEIVER
SLAVE
TWSTA
TWSTA
TWSTA
TWSTA
TWSTA
1
0
0
0
1
TWSTO
TWSTO
TWSTO
TWSTO
TWSTO
Device 3
0
0
0
1
0
TWWC
TWWC
TWWC
TWWC
TWWC
X
X
X
X
X
........
Table
TWEN
TWEN
TWEN
TWEN
TWEN
Device n
88). In order to enter MT mode,
1
1
1
1
1
V
CC
–
0
–
0
–
0
–
0
–
0
ATmega128
R1
TWIE
TWIE
TWIE
TWIE
TWIE
R2
X
X
X
X
X
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