ATMEGA128-16AI Atmel, ATMEGA128-16AI Datasheet - Page 172

• Manufacturer Part Number: ATMEGA128-16AI
• Description: IC AVR MCU 128K 16MHZ 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q1167170A

AVR USART vs. AVR
UART – Compatibility
Clock Generation
172
ATmega128
The USART is fully compatible with the AVR UART regarding:
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However, the receive buffering has two improvements that will affect the compatibility in some
special cases:
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The following control bits have changed name, but have same functionality and register location:
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The clock generation logic generates the base clock for the transmitter and receiver. The
USART supports four modes of clock operation: Normal Asynchronous, Double Speed Asyn-
chronous, Master Synchronous, and Slave Synchronous mode. The UMSEL bit in USART
Control and Status Register C (UCSRC) selects between asynchronous and synchronous oper-
ation. Double speed (Asynchronous mode only) is controlled by the U2X found in the UCSRA
Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK
pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave
mode). The XCK pin is only active when using Synchronous mode.
Figure 80
Figure 80. Clock Generation Logic, Block Diagram
Signal description:
Bit locations inside all USART registers
Baud Rate Generation
Transmitter Operation
Transmit Buffer Functionality
Receiver Operation
A second buffer register has been added. The two buffer registers operate as a circular FIFO
buffer. Therefore the UDR must only be read once for each incoming data! More important is
the fact that the error flags (FE and DOR) and the ninth data bit (RXB8) are buffered with the
data in the receive buffer. Therefore the status bits must always be read before the UDR
Register is read. Otherwise the error status will be lost since the buffer state is lost.
The receiver Shift Register can now act as a third buffer level. This is done by allowing the
received data to remain in the serial Shift Register (see
full, until a new start bit is detected. The USART is therefore more resistant to Data OverRun
(DOR) error conditions.
CHR9 is changed to UCSZ2
OR is changed to DOR
shows a block diagram of the clock generation logic.
DDR_XCK
XCK
Pin
xcko
xcki
OSC
Down-Counter
Prescaling
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/ 2
/ 4
Figure
/ 2
79) if the buffer registers are
DDR_XCK
U2X
0
1
0
1
0
1
1
0
UMSEL
2467V–AVR–02/11
txclk
rxclk