ATMEGA128-16AI Atmel, ATMEGA128-16AI Datasheet - Page 63

IC AVR MCU 128K 16MHZ 64-TQFP

ATMEGA128-16AI

Manufacturer Part Number
ATMEGA128-16AI
Description
IC AVR MCU 128K 16MHZ 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128-16AI

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Q1167170A

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Moving Interrupts
Between Application
and Boot Space
MCU Control Register
– MCUCR
2467V–AVR–02/11
The General Interrupt Control Register controls the placement of the interrupt vector table.
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash
memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot
Loader section of the flash. The actual address of the start of the Boot Flash section is deter-
mined by the BOOTSZ fuses. Refer to the section
Self-Programming” on page 273
tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note:
Bit
Read/Write
Initial Value
$F049
$F04A
$F04B
If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If interrupt vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section
Write Self-Programming” on page 273
SRE
R/W
7
0
SRW10
out
sei
<instr>
R/W
6
0
SPL,r16
R/W
SE
5
0
xxx
for details. To avoid unintentional changes of interrupt vector
SM1
R/W
4
0
; Enable interrupts
for details on Boot Lock bits.
SM0
R/W
3
0
“Boot Loader Support – Read-While-Write
SM2
R/W
2
0
“Boot Loader Support – Read-While-
IVSEL
R/W
1
0
IVCE
R/W
ATmega128
0
0
MCUCR
63

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