ATMEGA128-16AI Atmel, ATMEGA128-16AI Datasheet - Page 152
ATMEGA128-16AI
Manufacturer Part Number
ATMEGA128-16AI
Description
IC AVR MCU 128K 16MHZ 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16AI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Q1167170A
Available stocks
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Part Number:
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Phase Correct PWM
Mode
152
ATmega128
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR2 Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be
a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a
constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC2 to toggle its logical level on each compare match (COM21:0 = 1). The waveform
generated will have a maximum frequency of f
ture is similar to the OC2 toggle in CTC mode, except the double buffer feature of the output
compare unit is enabled in the fast PWM mode.
The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM
waveform generation option. The phase correct PWM mode is based on a dual-slope operation.
The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-
inverting Compare Output mode, the output compare (OC2) is cleared on the compare match
between TCNT2 and OCR2 while counting up, and set on the compare match while downcount-
ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has
lower maximum operation frequency than single slope operation. However, due to the symmet-
ric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
The PWM resolution for the phase correct PWM mode is fixed to 8 bits. In phase correct PWM
mode the counter is incremented until the counter value matches Max When the counter
reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one
timer clock cycle. The timing diagram for the phase correct PWM mode is shown on
The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal
line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2.
f
OCnPWM
OC2
=
= f
----------------- -
N 256
f
clk_I/O
⋅
clk_I/O
/2 when OCR2 is set to zero. This fea-
2467V–AVR–02/11
Figure
67.
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