ATMEGA128-16AI Atmel, ATMEGA128-16AI Datasheet - Page 183

• Manufacturer Part Number: ATMEGA128-16AI
• Description: IC AVR MCU 128K 16MHZ 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q1167170A

Parity Checker
Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing
Flushing the Receive
Buffer
2467V–AVR–02/11
The parity checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity
check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the parity
checker calculates the parity of the data bits in incoming frames and compares the result with
the parity bit from the serial frame. The result of the check is stored in the receive buffer together
with the received data and stop bits. The Parity Error (UPE) flag can then be read by software to
check if the frame had a Parity Error.
The UPE bit is set if the next character that can be read from the receive buffer had a parIty
Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is
valid until the Receive buffer (UDR) is read.
receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the receiver will no
longer override the normal function of the RxD port pin. The receiver buffer FIFO will be flushed
when the receiver is disabled. Remaining data in the buffer will be lost
The receiver buffer FIFO will be flushed when the receiver is disabled, i.e. the buffer will be emp-
tied of its contents. Unread data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDR I/O location until the RXC flag is
cleared. The following code example shows how to flush the receive buffer.
Note:
Assembly Code Example
C Code Example
USART_Flush:
void USART_Flush( void )
{
}
sbis UCSRA, RXC
ret
in
rjmp USART_Flush
unsigned char dummy;
while ( UCSRA & (1<<RXC) ) dummy = UDR;
1.
“About Code Examples” on page
The USART includes a clock recovery and a data recovery unit for handling asynchronous
data reception. The clock recovery logic is used for synchronizing the internally generated
baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery
logic samples and low pass filters each incoming bit, thereby improving the noise immunity of
the receiver. The asynchronous reception operational range depends on the accuracy of the
internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
r16, UDR
(1)
(1)
8.
ATmega128
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