ATMEGA128-16AI Atmel, ATMEGA128-16AI Datasheet - Page 122

IC AVR MCU 128K 16MHZ 64-TQFP

ATMEGA128-16AI

Manufacturer Part Number
ATMEGA128-16AI
Description
IC AVR MCU 128K 16MHZ 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128-16AI

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Q1167170A

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Compare Match
Output Unit
Compare Output Mode
and Waveform
Generation
122
ATmega128
The Compare Output mode (COMnx1:0) bits have two functions. The waveform generator uses
the COMnx1:0 bits for defining the output compare (OCnx) state at the next compare match.
Secondly the COMnx1:0 bits control the OCnx pin output source.
schematic of the logic affected by the COMnx1:0 bit setting. The I/O registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR
and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx
state, the reference is for the internal OCnx Register, not the OCnx pin. If a system Reset occur,
the OCnx Register is reset to “0”.
Figure 50. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the output compare (OCnx) from the Waveform
Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The data direction
register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visible
on the pin. The port override function is generally independent of the waveform generation
mode, but there are some exceptions. Refer to
The design of the output compare pin logic allows initialization of the OCnx state before the out-
put is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of
operation.
The COMnx1:0 bits have no effect on the Input Capture unit.
The waveform generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COMnx1:0 = 0 tells the waveform generator that no action on the
OCnx Register is to be performed on the next compare match. For compare output actions in the
non-PWM modes refer to
133, and for phase correct and phase and frequency correct PWM refer to
133.
A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOCnx strobe bits.
See “16-bit Timer/Counter Register Description” on page 132.
COMnx1
COMnx0
FOCnx
clk
I/O
Waveform
Generator
Table 58 on page
D
D
D
PORT
OCnx
DDR
132. For fast PWM mode refer to
Table
Q
Q
Q
58,
Table 59
1
0
Figure 50
and
Table 60
shows a simplified
Table 60 on page
Table 59 on page
OCnx
Pin
for details.
2467V–AVR–02/11

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