ATMEGA128-16AI Atmel, ATMEGA128-16AI Datasheet

IC AVR MCU 128K 16MHZ 64-TQFP

ATMEGA128-16AI

Manufacturer Part Number
ATMEGA128-16AI
Description
IC AVR MCU 128K 16MHZ 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128-16AI

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Q1167170A

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Features
High-performance, Low-power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
– 128Kbytes of In-System Self-programmable Flash program memory
– 4Kbytes EEPROM
– 4Kbytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Up to 64Kbytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
– 2.7 - 5.5V ATmega128L
– 4.5 - 5.5V ATmega128
– 0 - 8MHz ATmega128L
– 0 - 16MHz ATmega128
Capture Mode
Extended Standby
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
®
AVR
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 128KBytes
In-System
Programmable
Flash
ATmega128
ATmega128L
Rev. 2467V–AVR–02/11

Related parts for ATMEGA128-16AI

ATMEGA128-16AI Summary of contents

Page 1

... I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V ATmega128L – 4.5 - 5.5V ATmega128 • Speed Grades – 8MHz ATmega128L – 16MHz ATmega128 ® ® AVR 8-bit Microcontroller (1) 8-bit Microcontroller with 128KBytes In-System ...

Page 2

... PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6 Note: Overview The Atmel enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega128 achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ATmega128 ...

Page 3

... GENERAL PURPOSE REGISTERS ALU STATUS REGISTER DATA REGISTER DATA DIR. PORTB REG. PORTB PORTB DRIVERS PB0 - PB7 ATmega128 PC0 - PC7 PORTC DRIVERS DATA REGISTER DATA DIR. PORTC REG. PORTC 8-BIT DATA BUS CALIB. OSC INTERNAL OSCILLATOR OSCILLATOR WATCHDOG TIMER OSCILLATOR TIMING AND ...

Page 4

... Atmel ATmega128 is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications. The ATmega128 device is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...

Page 5

... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega128 as listed on 73. Port C (PC7..PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...

Page 6

... PG3 and PG4 are oscillator pins. ATmega128 6 The ATmega128 is by default shipped in ATmega103 compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode is disabled. ...

Page 7

... By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Pro- gramming mode. PEN has no function during normal operation. 2467V–AVR–02/11 , even if the ADC is not used. If the ADC is used, it should be connected ATmega128 Table 19 on page CC 7 ...

Page 8

... For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega128 8 1. ...

Page 9

... AVR ® core architecture in general. The main function of the Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega128 Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog Timer ALU ...

Page 10

... The lower the interrupt vector address, the higher the priority. The I/O memory space contains 64 addresses which can be accessed directly the Data Space locations following those of the Register file, $20 - $5F. In addition, the ATmega128 has Extended I/O space from $60 - $FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ALU – ...

Page 11

... Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 4 on page 12 CPU. 2467V–AVR–02/11 ⊕ V shows the structure of the 32 general purpose working registers in the ATmega128 11 ...

Page 12

... Data Space. The three indirect address registers X, Y, and Z are described in Figure 5. The X-, Y-, and Z-registers X - register Y - register Z - register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set Reference for details). ATmega128 … R13 ...

Page 13

... Bit 0 – RAMPZ0: Extended RAM Page Z-pointer The RAMPZ Register is normally used to select which 64K RAM Page is accessed by the Z- pointer. As the ATmega128 does not support more than 64K of SRAM memory, this register is used only to select which page in the program memory is accessed when the ELPM/SPM instruction is used ...

Page 14

... The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. ATmega128 14 shows the parallel instruction fetches and instruction executions enabled by the Har- ...

Page 15

... SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ 2467V–AVR–02/11 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ATmega128 15 ...

Page 16

... A return from an interrupt handling routine takes four clock cycles. During these 4-clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incre- mented by two, and the I-bit in SREG is set. ATmega128 16 ; set global interrupt enable 2467V–AVR–02/11 ...

Page 17

... Boot Program section and Application Program section. Memory The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega128 Program Counter (PC bits wide, thus addressing the 64K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in 273 ...

Page 18

... Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O space does not exist when the ATmega128 is in the ATmega103 com- patibility mode. ...

Page 19

... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O registers, and the 4096bytes of internal data SRAM in the ATmega128 are all accessible through all these addressing modes. The Register file is described in Figure 9. Data Memory Map 2467V– ...

Page 20

... T1 clk CPU Address Compute Address Data WR Data RD Memory access instruction ® ® AVR ATmega128 contains 4Kbytes of data EEPROM memory organized as a contains a detailed description on EEPROM programming for details on how to avoid problems in these situations – – – – EEAR7 EEAR6 EEAR5 ...

Page 21

... Initial Value • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega128 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt ...

Page 22

... EEPROM, nor to change the EEAR Register. The calibrated Oscillator is used to time the EEPROM accesses. gramming time for EEPROM access from the CPU. Table 2. EEPROM Programming Time EEPROM Write (from CPU) Note: ATmega128 22 Number of Calibrated RC Symbol Oscillator Cycles 1. Uses 1MHz clock, independent of CKSEL-fuse settings. ...

Page 23

... Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); ATmega128 23 ...

Page 24

... CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD reset occurs while a write oper- ATmega128 24 r16,EEDR ; ...

Page 25

... When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...

Page 26

... Lower sector SRW01 SRW00 SRL[2..0] Upper sector (0-60K x 8) SRW11 SRW10 0xFFFF ATmega128 in non ATmega103 compatibility mode: Memory Configuration A is available (Memory Configuration B N/A) ATmega128 in ATmega103 compatibility mode: Memory Configuration B is available (Memory Configuration A N/A) Memory Configuration B 0x0000 Internal memory 0x0FFF 0x1000 ...

Page 27

... Figure 12 illustrates how to connect an external SRAM to the AVR using an octal ). ns. Refer LAXX_LD ) must not exceed address valid to ALE low (t SU AD7:0 ALE AVR A15 ATmega128 “I/O Ports” on page ). “External Data Memory Timing” LLAXX_ST D[7:0] A[7: SRAM A[15: 65. The XMEM ...

Page 28

... The most important parameters are the access time for the external memory compared to the set-up requirement of the ATmega128. The access time for the External Memory is defined to be the time from receiving the chip select/address until the data of this address actually is driven on the bus ...

Page 29

... Address DA7:0 (XMBK = 1) Prev. data Address RD 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal or external). ATmega128 Address XX Data Data Data ...

Page 30

... Control Register A – Bit XMCRA Read/Write Initial Value • Bit 7 – Res: Reserved Bit This is a reserved bit and will always read as zero. When writing to this address location, write this bit to zero for compatibility with future devices. ATmega128 CPU ALE A15:8 Prev ...

Page 31

... Wait two cycles during read/write and wait one cycle before driving out new address (lower/upper sector). For further details of the timing and wait-states of the External Memory Interface, see Figures 13 through Figures 16 for how the setting of the SRW bits affects the timing. ATmega128 Table 3 and Figure 11. By ...

Page 32

... This is illustrated in refers to the ATmega103 compatibility mode, configuration A to the non-compatible mode. When the device is set in ATmega103 compatibility mode, the internal address space is 4,096 bytes. This implies that the first 4,096 bytes of the external memory can be accessed at ATmega128 ...

Page 33

... Memory Configuration A AVR Memory Map External 32K SRAM 0x0000 Internal Memory 0x10FF 0x1100 External 0x7FFF 0x8000 Memory 0x90FF 0x9100 (Unused) 0xFFFF ATmega128 Memory Configuration B AVR Memory Map 0x0000 0x0000 Internal Memory 0x0FFF 0x1000 0x10FF 0x1100 External 0x7FFF 0x7FFF 0x8000 Memory 0x8FFF ...

Page 34

... DDRC = 0xFF; PORTC = 0x00; XMCRB = (1<<XMM1) | (1<<XMM0 0xaa; XMCRB = 0x00 0x55; } Note: Care must be exercised using this option as most of the memory is masked away. ATmega128 34 (1) r16, 0xFF DDRC, r16 r16, 0x00 PORTC, r16 r16, (1<<XMM1)|(1<<XMM0) XMCRB, r16 ...

Page 35

... I/O Control Unit clk ASY Clock Multiplexer Timer/Counter External RC Oscillator Oscillator External clock is halted, enabling TWI address reception in all sleep modes. I/O ATmega128 CPU Core RAM clk ADC clk CPU clk FLASH Reset Logic Watchdog Timer Source clock Watchdog clock Watchdog ...

Page 36

... The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 6. Device Clocking Options Select Device Clocking Option External Crystal/Ceramic Resonator External Low-frequency Crystal External RC Oscillator Calibrated Internal RC Oscillator External Clock ATmega128 XDIVEN XDIV6 XDIV5 ...

Page 37

... In-System or Parallel Programmer. 2467V–AVR–02/11 1. For all fuses “1” means unprogrammed while “0” means programmed. 333. = 5.0V) Typical Time-Out (V CC 4.1ms 65ms ATmega128 = 3.0V) Number of Cycles CC 4.3ms 4K (4,096) 69ms 64K (65,536) Table 7. “ ...

Page 38

... The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8. Crystal Oscillator Operating Modes CKOPT Note: The CKSEL0 fuse together with the SUT1..0 fuses select the start-up times as shown in ATmega128 Frequency Range CKSEL3..1 (MHz) (1) 101 0.4 - 0.9 110 0 ...

Page 39

... Reset Power-save ( 4.1ms ( 65ms 32K CK 65ms 1. These options should only be used if frequency stability at start-up is not important for the application. ATmega128 Additional Delay from Reset (V = 5.0V) Recommended Usage CC 4.1ms Ceramic resonator, fast rising power 65ms Ceramic resonator, slowly rising power – ...

Page 40

... The operating mode is selected by the fuses CKSEL3..0 as shown in Table 11. External RC Oscillator Operating Modes When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 12. Table 12. Start-Up Times for the External RC Oscillator Clock Selection SUT1.. Note: ATmega128 CKSEL3..0 0101 0110 0111 1000 ...

Page 41

... CAL7 CAL6 CAL5 CAL4 R/W R/W R/W R/W Device Specific Calibration Value OSCCAL Register is not available in ATmega103 compatibility mode. ATmega128 Table 13. If selected, it will operate with no external and Temperature. When this Oscillator is CC Nominal Frequency (MHz) 1.0 2.0 4.0 8.0 Reset ( ...

Page 42

... When applying an external clock required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior required to ensure that the MCU is kept in Reset during such changes in the clock frequency. ATmega128 42 Table Min Frequency in Percentage of ...

Page 43

... No external capacitors are needed. The Oscillator is opti- mized for use with a 32.768kHz watch crystal. Applying an external clock source to TOSC1 is not recommended. Note: 2467V–AVR–02/11 The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator and the internal capacitors have the same nominal value of 36pF. ATmega128 43 ...

Page 44

... Bits 4..2 – SM2..0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the six available sleep modes as shown in Table 17. Sleep Mode Select SM2 Note: ATmega128 44 presents the different clock systems in the ATmega128, and their distribu SRE SRW10 SE SM1 R/W R/W R/W R ...

Page 45

... Timer/Counter0 if clocked asynchronously. 2467V–AVR–02/11 and clk , while allowing the other clocks to run. CPU FLASH “Clock Sources” on page , allowing operation only of asynchronous ASY ATmega128 , clk , and clk , while allowing I/O CPU FLASH “External Interrupts” on page 89 36. ...

Page 46

... CPU FLASH IO Idle X ADC Noise Reduction Power- down Power- save (1) Standby Extended (1) Standby Notes: 1. External Crystal or resonator selected as clock source bit in ASSR is set 3. Only INT3:0 or level interrupt INT7:4 ATmega128 46 Oscillators Main Clock Timer Source Osc clk Enabled Enabled INT7:0 ADC ASY ( ( (2) ...

Page 47

... ADC clock (clk I/O “Digital Input Enable and Sleep Modes” on page 69 /2, the input buffer will use excessive power. CC ATmega128 “Analog to Digital Converter” on page 230 for details on how to for details on how to “Internal Volt- ) are stopped, the input buffers of the ADC “ ...

Page 48

... Note that the TDI pin for the next device in the scan chain con- tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. ATmega128 48 2467V–AVR–02/11 ...

Page 49

... JTAG system. Refer to the section Boundary-scan” on page 252 2467V–AVR–02/11 defines the electrical parameters of the reset circuitry. “Clock Sources” on page ® ® AVR ATmega128 has five sources of reset: ). POT ) and the Brown-out Detector is enabled. BOT for details. ATmega128 Figure 22 shows the reset 36 ...

Page 50

... Figure 22. Reset Logic Table 19. Reset Characteristics Symbol V POT V RST t RST V BOT t BOD V HYST Notes: ATmega128 PEN L Q Pull-up Resistor Power-On Reset Circuit Brown-Out BODEN Reset Circuit BODLEVEL Pull-up Resistor SPIKE RESET Reset Circuit FILTER JTAG Reset Watchdog Register Timer Watchdog Oscillator ...

Page 51

... BOT this is the case, the device is tested down to V antees that a Brown-out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL=1for ATmega128L and BODLEVEL=0 for ATmega128. BODLEVEL=1 is not applicable forATmega128 Table 19. The POR is activated whenever V rise ...

Page 52

... Figure 25. External Reset During Operation Brown-out Detection ATmega128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spike free Brown-out Detection. The ...

Page 53

... MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. Internal Voltage ATmega128 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V ref- Reference erence to the ADC is generated from the internal bandgap reference. 2467V– ...

Page 54

... Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega128 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, 3 different safety levels are selected by the Fuses M103C and WDTON as shown in Table 21 ...

Page 55

... Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega128 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...

Page 56

... The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch- dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 22. Watchdog Timer Prescale Select WDP2 ATmega128 56 See “Timed Sequences for Changing the Configuration of the Watchdog Table 22. Number of WDT WDP1 WDP0 Oscillator Cycles 0 0 16K (16,384) 0 ...

Page 57

... WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret /* Reset WDT*/ __watchdog_reset(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; ATmega128 page 55 (WDE bit description) must be followed. 57 ...

Page 58

... WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. ATmega128 58 2467V–AVR–02/11 ...

Page 59

... Interrupts This section describes the specifics of the interrupt handling as performed in Atmel ATmega128. For a general explanation of the AVR interrupt handling, refer to rupt Handling” on page Interrupt Vectors in ATmega128 Table 23. Reset and Interrupt Vectors Vector No 2467V–AVR–02/11 14. Program (2) Address Source Interrupt Definition ...

Page 60

... This is also the case if the Reset Vector is in the Application section while the interrupt vectors are in the Boot section or vice versa. Table 24. Reset and Interrupt Vectors Placement BOOTRST Note: ATmega128 60 Program (2) Address Source Interrupt Definition (3) $003C USART1, RX ...

Page 61

... The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega128 is: Address LabelsCode $0000 $0002 $0004 $0006 $0008 $000A $000C $000E $0010 $0012 $0014 $0016 $0018 $001A $001C $001E $0020 $0022 $0024 $0026 $0028 $002A $002C $002E ...

Page 62

... MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address ; .org $F000 $F000 $F002 $F004 ... $F044 $F046 $F047 $F048 ATmega128 62 Comments RESET:ldi r16,high(RAMEND); Main program start out SPH,r16 ; Set stack pointer to top of RAM ldi r16,low(RAMEND) out SPL,r16 sei ...

Page 63

... Application section. If interrupt vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Write Self-Programming” on page 273 ATmega128 ; Enable interrupts 3 2 ...

Page 64

... MCUCR, r16 ; Move interrupts to boot flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret C Code Example void Move_interrupts(void Enable change of interrupt vectors */ MCUCR = (1<<IVCE); /* Move interrupts to boot flash section */ MCUCR = (1<<IVSEL); } ATmega128 64 2467V–AVR–02/11 ...

Page 65

... Read-Modify-Write functionality when used as general digital and Ground as indicated in CC for a complete list of parameters. Pxn C PIN “Register Description for I/O Ports” on page 70. Refer to the individual module sections for a full description of the alter- ATmega128 Figure 29. Refer to “Electri Logic See Figure "General Digital I/O" for Details 86 ...

Page 66

... If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output ATmega128 66 (1) PUD: ...

Page 67

... X Output Figure 30, the PINxn Register bit and the preceding latch consti- and t pd,max SYSTEM CLK INSTRUCTIONS XXX SYNC LATCH PINxn r17 ATmega128 Comment No Tri-state (Hi-Z) Pxn will source current if ext. pulled Yes low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) ...

Page 68

... When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in clock. In this case, the delay t Figure 32. Synchronization when Reading a Software Assigned Pin Value INSTRUCTIONS ATmega128 68 and single signal transition on the pin will be delayed pd,max pd,min Figure 32. The out instruction sets the “ ...

Page 69

... Figure 30, the digital input signal can be clamped to ground at the input of the /2. CC ATmega128 “Alternate Port Functions” on page 70. 69 ...

Page 70

... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 33. Alternate Port Functions Note: ATmega128 70 or GND is not recommended, since this may cause excessive currents if the pin is CC ...

Page 71

... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. Analog This is the Analog Input/output to/from alternate functions. Input/output The signal is connected directly to the pad, and can be used bi-directionally. ATmega128 Fig- 71 ...

Page 72

... PA3 PA2 PA1 PA0 Table 28 Figure 33 on page Table 28. Overriding Signals for Alternate Functions in PA7..PA4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: ATmega128 TSM – – – R for more details about this feature. Alternate Function ...

Page 73

... OC0 (Output Compare and PWM Output for Timer/Counter0) MISO (SPI Bus Master Input/Slave Output) MOSI (SPI Bus Master Output/Slave Input) SCK (SPI Bus Serial Clock) SS (SPI Slave Select input) 1. OC1C not applicable in ATmega103 compatibility mode. ATmega128 PA1/AD1 PA0/AD0 SRE SRE ~(WR | ADA) • ...

Page 74

... When the pin is forced input, the pull-up can still be controlled by the PORTB0 bit. Table 31 Figure 33 on page while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. ATmega128 74 and Table 32 relate the alternate functions of Port B to the overriding signals shown in 70. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, 2467V– ...

Page 75

... PORTB3 • PUD PORTB2 • PUD SPE • MSTR SPE • MSTR 0 0 SPE • MSTR SPE • MSTR SPI SLAVE OUTPUT SPI MSTR OUTPUT SPI MSTR INPUT SPI SLAVE INPUT – – ATmega128 PB5/OC1A PB4/OC0 OC1A ENABLE OC0 ENABLE OC1A OC0B – ...

Page 76

... Alternate Functions of In ATmega103 compatibility mode, Port C is output only. The ATmega128 is by default shipped Port C in compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode is dis- abled ...

Page 77

... Interrupt2 Input or UART1 Receive Pin) (1) INT1/SDA (External Interrupt1 Input or TWI Serial DAta) (1) INT0/SCL (External Interrupt0 Input or TWI Serial CLock) 1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility mode. ATmega128 (1) PC1/A9 PC0/A8 SRE • (XMM<7) SRE • (XMM< SRE • (XMM<7) SRE • ...

Page 78

... I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to sup- press spikes shorter than 50ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. Table 37 Figure 33 on page ATmega128 78 and Table 38 relates the alternate functions of Port D to the overriding signals shown in 70. 2467V– ...

Page 79

... When enabled, the Two-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. ATmega128 PD5/XCK1 PD4/ICP1 ...

Page 80

... The OC3A pin is also the output pin for the PWM mode timer function. • AIN0/XCK0 – Port E, Bit 2 AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. ATmega128 80 Alternate Function (1) INT7/ICP3 ...

Page 81

... Synchronous mode. • PDO/TXD0 – Port E, Bit 1 PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the ATmega128. TXD0, UART0 Transmit pin. • PDI/RXD0 – Port E, Bit 0 PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the ATmega128 ...

Page 82

... TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. The TDO pin is tri-stated unless TAP states that shift out data are entered. • TMS, ADC5 – Port F, Bit 5 ADC5, Analog to Digital Converter, Channel 5 ATmega128 82 PE3/AIN1/OC3A PE2/AIN0/XCK0 0 ...

Page 83

... JTAGEN 0 SHIFT_IR + SHIFT_DR 0 JTAGEN 0 TDO JTAGEN JTAGEN 0 0 – – TDI/ADC7 INPUT ADC6 INPUT PF3/ADC3 PF2/ADC2 – – ADC3 INPUT ADC2 INPUT ATmega128 . PF5/ADC5/TMS PF4/ADC4/TCK JTAGEN JTAGEN 1 1 JTAGEN JTAGEN JTAGEN JTAGEN 0 0 – – TMS/ADC5 TCK/ADC4 INPUT INPUT PF1/ADC1 PF0/ADC0 ...

Page 84

... PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega128 84 ® AVR ® ATmega103 compatibility mode, only the alternate functions are the defaults for Alternate Function TOSC1 (RTC Oscillator Timer/Counter0) TOSC2 (RTC Oscillator Timer/Counter0) ALE (Address Latch Enable to external memory) RD (Read strobe to external memory) ...

Page 85

... Table 47. Overriding Signals for Alternate Functions in PG0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 2467V–AVR–02/11 ATmega128 PG0/WR SRE 0 SRE 1 SRE – – 85 ...

Page 86

... Initial Value Port B Input Pins Bit Address – PINB Read/Write Initial Value Port C Data Register – Bit PORTC Read/Write Initial Value Port C Data Direction Bit Register – DDRC Read/Write Initial Value ATmega128 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 R/W R/W R/W R/W 0 ...

Page 87

... DDE6 DDE5 DDE4 R/W R/W R/W R PINE7 PINE6 PINE5 PINE4 N/A N/A N/A N PORTF7 PORTF6 PORTF5 PORTF4 R/W R/W R/W R ATmega128 PINC3 PINC2 PINC1 PINC0 N/A N/A N/A N PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R/W R DDD3 DDD2 DDD1 DDD0 R/W R/W ...

Page 88

... Port G Input Pins Bit Address – PING Read/Write Initial Value Note that PORTG, DDRG, and PING are not available in ATmega103 compatibility mode. In the ATmega103 compatibility mode Port G serves its alternate functions only (TOSC1, TOSC2, WR, RD and ALE). ATmega128 DDF7 DDF6 DDF5 ...

Page 89

... If the level is sampled twice by the Watchdog Oscillator clock but ISC31 ISC30 ISC21 ISC20 R/W R/W R/W R ® AVR Table 48. Edges on INT3..INT0 are registered asynchro- ATmega128 35. Low level interrupts and the 318. The MCU will “Clock Systems and ISC11 ISC10 ISC01 ISC00 EICRA R/W R/W R/W R ® ...

Page 90

... If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. Table 50. Interrupt Sense Control ISCn1 Note: ATmega128 90 (1) ISCn0 Description 0 The low level of INTn generates an interrupt request. 1 Reserved 0 The falling edge of INTn generates asynchronously an interrupt request ...

Page 91

... Enable and Sleep Modes” on page 69 2467V–AVR–02/ INT7 INT6 INT5 INT4 INT3 R/W R/W R/W R/W R INTF7 INTF6 INTF5 INTF4 INTF3 R/W R/W R/W R/W R for more information. ATmega128 INT2 INT1 IINT0 EIMSK R/W R/W R INTF2 INTF1 IINTF0 EIFR R/W R/W R “Digital Input 91 ...

Page 92

... TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac- ATmega128 92 “Pin Configurations” on page “8-bit Timer/Counter Register Description” on page ...

Page 93

... MCU clock, clk T0 109. DATA BUS count clear TCNTn Control Logic direction bottom ATmega128 See “Output Compare 106. For details on clock sources and prescaler, see TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler top . When the AS0 I/O “ ...

Page 94

... WGM01:0 bits and compare output mode (COM01:0) bits. The max and bottom signals are used by the waveform generator for han- dling the special cases of the extreme values in some modes of operation on page ATmega128 94 Increment or decrement TCNT0 by 1. Selects between increment and decrement. ...

Page 95

... The setup of the OC0 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0 value is to use the force output compare 2467V–AVR–02/11 DATA BUS OCRn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 COMn1:0 ATmega128 TCNTn OCFn (Int.Req.) OCxy 95 ...

Page 96

... PWM refer to A change of the COM01:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0 strobe bits. ATmega128 96 COMn1 Waveform ...

Page 97

... Timing Diagrams” on page TOV0 flag, the timer resolution can be increased by software. There TOV0 Figure ATmega128 101. ) will be set in the same TOV0 flag in this case behaves like a ninth 38. The counter value (TCNT0) OCn Interrupt Flag Set (COMn1 ...

Page 98

... The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in gram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0. ATmega128 98 f clk_I/O f ...

Page 99

... PWM mode. 2467V–AVR–02/ set each time the counter reaches Max If the interrupt TOV0 Table 54 on page f = OCnPWM = f oc0 ATmega128 OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set (COMn1 (COMn1 104). The actual OC0 value f clk_I/O ----------------- - ⋅ ...

Page 100

... The PWM waveform is generated by clearing (or setting) the OC0 Register at the compare match between OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0 Register at compare match between OCR0 and TCNT0 when the counter decrements. The ATmega128 100 set each time the counter reaches BOTTOM ...

Page 101

... Timer/Counter operation. The Timer/Counter contains timing data for basic Timer/Counter operation. The figure shows the I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega128 f clk_I/O = ----------------- - ⋅ N 510 Figure 40. When the OCR0 value is MAX the ) is therefore shown as a clock enable signal ...

Page 102

... TCNTn TOVn Figure 43 Figure 43. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f clk clk (clk TCNTn OCRn OCFn Figure 44 ATmega128 102 I/O Tn /8) I/O MAX - 1 shows the setting of OCF0 in all modes except CTC mode. I/O Tn /8) I/O OCRn - 1 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. ...

Page 103

... Pulse Width Modulation (PWM) modes. See page 97. 2467V–AVR–02/11 /8) I/O Tn /8) I/O TOP - FOC0 WGM00 COM01 COM00 W R/W R/W R ATmega128 TOP BOTTOM BOTTOM + 1 TOP WGM01 CS02 CS01 CS00 R/W R/W R/W R Table 52 and “Modes of Operation” on TCCR0 103 ...

Page 104

... CTC mode (non-PWM). Table 53. Compare Output Mode, non-PWM Mode COM01 Table 54 mode. Table 54. Compare Output Mode, Fast PWM Mode COM01 Note: Table 55 PWM mode. ATmega128 104 (1) (1) WGM01 WGM00 Timer/Counter (CTC0) (PWM0) Mode of Operation 0 0 Normal 0 1 PWM, Phase Correct 1 ...

Page 105

... T0S clk 0 1 /128 (From prescaler) T0S 1 0 clk /256 (From prescaler clk /1024 (From prescaler TCNT0[7:0] R/W R/W R/W R OCR0[7:0] R/W R/W R/W R ATmega128 (1) “Phase Correct PWM Mode” on page TCNT0 R/W R/W R/W R OCR0 R/W R/W R/W R Table 105 ...

Page 106

... Clear the Timer/Counter0 interrupt flags. 6. Enable interrupts, if needed. • The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter0 operation. The CPU main clock frequency must be more than four times the Oscillator frequency. ATmega128 106 – ...

Page 107

... The recommended procedure for reading TCNT0 is thus as follows: 1. Write any value to either of the registers OCR0 or TCCR0. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT0. 2467V–AVR–02/11 ) again becomes active, TCNT0 will read as the previous I/O ATmega128 107 ...

Page 108

... Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter- rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00. ATmega128 108 7 6 ...

Page 109

... By setting the AS0 bit in ASSR, Timer/Counter0 is asynchronously clocked I/O /256, and clk /1024. Additionally, clk T0S T0S TSM – – R ATmega128 10-BIT T/C PRESCALER 0 TIMER/COUNTER0 CLOCK SOURCE clk T0 . clk is by default connected to the main T0 T0 /8, clk T0S as well as 0 (stop) may be selected. T0S – ...

Page 110

... ATmega128 110 • Bit 1 – PSR0: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be reset. This bit is normally cleared immediately by hardware. If this bit is written when Timer/Counter0 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. 2467V– ...

Page 111

... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the 2467V–AVR–02/11 ® AVR ® ATmega103 compatibility mode, only one 16-bit Timer/Counter is “Pin Configurations” on page “16-bit Timer/Counter Register Description” on page ATmega128 Figure 46. For the actual 2. CPU accessible I/O Registers, 132. 111 ...

Page 112

... The output from the clock select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCRnA/B/C) are compared with the Timer/Counter value at all time. The result of the compare can be used by the waveform gener- ator to generate a PWM or variable frequency output on the Output Compare Pin (OCnA/B/C). ATmega128 112 Count Clear ...

Page 113

... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCRnA or ICRn Register. The assignment is dependent of the mode of operation. ATmega128 (See 113 ...

Page 114

... Timer Regis- ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. ATmega128 114 (1) (1) 1. See “ ...

Page 115

... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNTn into TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See “About Code Examples” on page 8. ATmega128 115 ...

Page 116

... If writing to more than one 16-bit register where the high byte is the same for all registers written, Temporary High Byte then the high byte only needs to be written once. However, note that the same rule of atomic Register operation described previously also applies in this case. ATmega128 116 (1) (1) 1. See “About Code Examples” on page 8. ...

Page 117

... Signalize that TCNTn has reached maximum value. Signalize that TCNTn has reached minimum value (zero). ). The clk can be generated from an external or internal clock present or not. A CPU write overrides (has priority over) all counter clear ATmega128 TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 143 ...

Page 118

... I/O bit location. Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied ATmega128 118 DATA BUS ...

Page 119

... I/O bit location). For measuring frequency only, the clearing of the ICFn flag is not required (if an interrupt handler is used). 2467V–AVR–02/11 114. ATmega128 “Accessing 16-bit Registers” (Figure 59 on page 143). The edge detector is also ...

Page 120

... The double buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. ATmega128 120 123.) shows a block diagram of the output compare unit. The small “n” in the register and bit ...

Page 121

... The OCnx Register keeps its value even when changing between waveform generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. 2467V–AVR–02/11 114. ATmega128 “Accessing 16-bit Registers” 121 ...

Page 122

... PWM refer to 133. A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. ATmega128 122 COMnx1 Waveform COMnx0 ...

Page 123

... Figure 51. CTC Mode, Timing Diagram 2467V–AVR–02/11 (See “Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page TCNTn OCnA (Toggle) Period 1 2 ATmega128 122.) Figure 51. The counter value (TCNTn) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 130 ...

Page 124

... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a compare match occurs. ATmega128 124 = f /2 when OCRnA is set to zero (0x0000). The waveform frequency is ...

Page 125

... OCRnx and TCNTn, and clearing (or setting) the OCnx Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). 2467V–AVR–02/ ATmega128 OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...

Page 126

... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx inter- rupt flag will be set when a compare match occurs. ATmega128 126 f clk_I/O ...

Page 127

... OCnx Register at compare match between OCRnx and TCNTn when 2467V–AVR–02/ Figure 53 illustrates, changing the TOP actively ATmega128 OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) ...

Page 128

... The diagram includes non- inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes repre- sent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a compare match occurs. ATmega128 128 f OCnxPCPWM 54) ...

Page 129

... The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). 2467V–AVR–02/ shows the output generated is, in contrast to the phase correct mode, symmetrical f OCnxPFCPWM ATmega128 OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set ...

Page 130

... TCNTn OCRnx OCFnx Figure 56 Figure 56. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx ATmega128 130 Figure 55 I/O Tn /1) I/O OCRnx - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O OCRnx - 1 ...

Page 131

... I/O clk Tn (clk /8) I/O TCNTn TOP - 1 TCNTn TOP - 1 (FPWM) (if used as TOP) OCRnx Old OCRnx Value ATmega128 TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 New OCRnx Value TOP - 2 ...

Page 132

... OCnC pin must be set in order to enable the output driver. When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM). Table 58. Compare Output Mode, non-PWM COMnA1/COMnB1/ COMnC1 ATmega128 132 COM1A1 ...

Page 133

... A special case occurs when COMnA1/COMnB1//COMnC1 is set. details. ATmega128 Description Normal port operation, OCnA/OCnB/OCnC disconnected. WGMn3:0 = 15: Toggle OCnA on Compare Match, OCnB/OCnC disconnected (normal port operation). For all other WGMn settings, normal port operation, OCnA/OCnB/OCnC disconnected. Clear OCnA/OCnB/OCnC on compare match, set OCnA/OCnB/OCnC at BOTTOM, ...

Page 134

... Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the location of these bits are compatible with previous versions of the timer. ATmega128 134 Table 61. Modes of operation supported by the Timer/Counter WGMn0 Timer/Counter Mode of (PWMn0) Operation 0 0 Normal 0 1 PWM, Phase Correct, 8-bit ...

Page 135

... The three clock select bits select the clock source to be used by the Timer/Counter, see 55 and 2467V–AVR–02/ ICNC1 ICES1 – WGM13 R/W R ICNC3 ICES3 – WGM33 R/W R Figure 56. ATmega128 WGM12 CS12 CS11 CS10 TCCR1B R/W R/W R/W R WGM32 CS32 CS31 CS30 TCCR3B R/W R/W R/W R Figure 135 ...

Page 136

... Timer on Compare Match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB/FOCnB bits are always read as zero. • Bit 4:0 – Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to zero when TCCRnC is written. ATmega128 136 CSn1 CSn0 Description clock source ...

Page 137

... R/W R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R/W R OCR1C[15:8] OCR1C[7:0] R/W R/W R/W R/W R OCR3A[15:8] OCR3A[7:0] R/W R/W R/W R/W R ATmega128 TCNT1H TCNT1L R/W R/W R TCNT3H TCNT3L R/W R/W R See “Accessing 16 OCR1AH OCR1AL R/W R/W R OCR1BH OCR1BL R/W R/W R ...

Page 138

... CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This Temporary Register is shared by all the other 16-bit registers. Timer/Counter Interrupt Mask Bit Register – TIMSK Read/Write Initial Value Note: ATmega128 138 OCR3B[15:8] OCR3B[7:0] R/W R/W ...

Page 139

... TICIE3 OCIE3A R R R/W R This register is not available in ATmega103 compatibility mode. “Interrupts” on page 59) is executed when the ICF3 flag, located in ETIFR, is set. “Interrupts” on page “Interrupts” on page ATmega128 OCIE3B TOIE3 OCIE3C OCIE1C R/W R/W R/W R 59) is executed when the OCF3A flag, located in ...

Page 140

... The setting of this flag is dependent of the WGMn3:0 bits setting. In normal and CTC modes, the TOV1 flag is set when the timer overflows. Refer to behavior when using another WGMn3:0 bit setting. ATmega128 140 59) is executed when the TOV3 flag, located in ETIFR, is set. “Interrupts” on page “ ...

Page 141

... This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register C (OCR1C). 2467V–AVR–02/ – – ICF3 OCF3A OCF3B R/W R/W R/W R/W R ATmega128 TOV3 OCF3C OCF1C ETIFR R/W R/W R Table 52 on page 104 for the TOV3 flag 141 ...

Page 142

... Note that a forced output compare (FOC1C) strobe will not set the OCF1C flag. OCF1C is automatically cleared when the Output Compare Match 1 C interrupt vector is exe- cuted. Alternatively, OCF1C can be cleared by writing a logic one to its bit location. ATmega128 142 2467V–AVR–02/11 ...

Page 143

... Alternatively, one of four taps from the prescaler can be used CLK_I/O /1024. CLK_I/O /clk ). The Tn pin is sampled once every system clock cycle by the pin synchroniza /clk I/O Synchronization ATmega128 CLK_I/O /clk pulse for each positive (CSn2 nega Edge Detector /8, f /64, CLK_I/O Figure ) ...

Page 144

... This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter3, Timer/Counter1, and Timer/Counter2 share the same prescaler and a reset of this prescaler will affect all three timers. ATmega128 144 < f /2) given a 50/50% duty cycle. Since the edge detector uses ...

Page 145

... Timer/Counter Register Description” on page TCCRn count clear Control Logic direction BOTTOM TOP Timer/Counter TCNTn = 0 = 0xFF = OCRn ATmega128 Figure 61. For the actual place- 2. CPU accessible I/O registers, including 156. TOVn (Int.Req.) Clock Select clk Tn Edge Tn Detector ( From Prescaler ) OCn (Int.Req.) ...

Page 146

... Tn top ATmega128 146 for details. The compare match event will also set the compare flag (OCF2) Table 63 are also used extensively throughout the document. The counter reaches the BOTTOM when it becomes 0x00. The counter reaches its MAXimum when it becomes 0xFF (decimal 255). ...

Page 147

... present or not. A CPU write overrides (has priority over) all counter clear or T2 149. DATA BUS OCRn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega128 Figure 63 shows a block diagram of the TCNTn OCFn (Int.Req.) OCn COMn1:0 147 ...

Page 148

... Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference is for the internal OC2 Register, not the OC2 pin System Reset occur, the OC2 Register is reset to “0”. ATmega128 148 Figure 64 shows a simplified schematic of ...

Page 149

... PORT D clk I/O See “8-bit Timer/Counter Register Description” on page 156. Table 65 on page 157. For fast PWM mode, refer to Table 67 on page “Compare Match Output Unit” on page Figure 154. ATmega128 Q 1 OCn DDR Table 66 on page 157. 148). 68, ...

Page 150

... The OC2 value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of f when OCR2 is set to zero (0x00). The waveform frequency is defined by the following equation: ATmega128 150 TOV 2 flag, the timer resolution can be increased by software ...

Page 151

... OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the coun- ter is cleared (changes from MAX to BOTTOM). 2467V–AVR–02/11 Figure 66. The TCNT2 value is in the timing diagram shown as a histo Table 66 on page ATmega128 OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set (COMn1 (COMn1 157) ...

Page 152

... The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. ATmega128 152 f clk_I/O ...

Page 153

... Table 67 on page f clk_I ----------------- - OCnPCPWM ⋅ N 510 Figure 67 OCn has a transition from high to low even though there Figure 67. When the OCR2A value is MAX the ATmega128 OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 157). The actual OC2 153 ...

Page 154

... TCNTn TOVn Figure 69 Figure 69. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 70 ATmega128 154 Figure 68 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ...

Page 155

... TCNTn (CTC) OCRn OCFn 2467V–AVR–02/11 I/O Tn /8) I/O OCRn - 1 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. /8) I/O Tn /8) I/O TOP - 1 ATmega128 OCRn OCRn + 1 OCRn Value TOP BOTTOM TOP /8) clk_I/O OCRn + 2 BOTTOM + 1 155 ...

Page 156

... However, note that the Data Direction Register (DDR) bit corresponding to the OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. normal or CTC mode (non-PWM). ATmega128 156 ...

Page 157

... TOP. See 152 for more details. CS21 CS20 Description clock source (Timer/Counter stopped clk /(No prescaling) I clk /8 (From prescaler) I clk /64 (From prescaler) I/O ATmega128 (1) “Fast PWM Mode” on page 151 (1) “Phase Correct PWM Mode” on page 157 ...

Page 158

... When the TOIE2 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR. ATmega128 158 CS21 CS20 ...

Page 159

... Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00. 2467V–AVR–02/ OCF2 TOV2 ICF1 OCF1A OCF1B R/W R/W R/W R/W R ATmega128 TOV1 OCF0 TOV0 TIFR R/W R/W R 159 ...

Page 160

... Timer/Counter units and the port B pin 7 output driver circuit. Figure 73. Output Compare Modulator, Schematic COM21 COM20 COM1C1 COM1C0 ( From Waveform Generator ) ( From Waveform Generator ) ATmega128 160 “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” and “8-bit Timer/Counter2 with PWM” on page Timer/Counter 1 OC1C Timer/Counter 2 ...

Page 161

... PB7 output is equal in both periods. 2467V–AVR–02/11 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate clk I/O OC1C OC2 PB7 PB7 1 (Period) ATmega128 2 3 Figure 161 ...

Page 162

... Serial The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the Atmel AVR ATmega128 and peripheral devices or between several AVR devices. The Peripheral ATmega128 SPI includes the following features: Interface – SPI • Full-duplex, Three-wire Synchronous Data Transfer • ...

Page 163

... Table 69. SPI Pin Overrides Pin MOSI MISO SCK SS 2467V–AVR–02/11 Table 69. For more details on automatic port overrides, refer to 70. (1) Direction, Master SPI User Defined Input User Defined User Defined ATmega128 SHIFT ENABLE “Alternate Port Direction, Slave SPI Input User Defined Input Input 163 ...

Page 164

... SPI_MasterTransmit(char cData Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) } Note: ATmega128 164 1. See “Alternate Functions of Port B” on page 73 direction of the user defined SPI pins. (1) r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) ...

Page 165

... Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; 1. See “About Code Examples” on page 8. ATmega128 165 ...

Page 166

... When the DORD bit is written to zero, the MSB of the data word is transmitted first. • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is set, MSTR will be cleared, ATmega128 166 7 6 ...

Page 167

... Figure 78 Leading edge 0 Rising 1 Falling Figure 77 Leading edge 0 Sample 1 Setup SPR1 SPR0 ATmega128 for an example. The CPOL functionality is summa- Trailing edge Falling Rising and Figure 78 for an example. The CPHA func- Trailing edge Setup Sample SCK Frequency osc osc osc 128 ...

Page 168

... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f lower. The SPI interface on the ATmega128 is also used for program memory and EEPROM down- loading or uploading. See SPI Data Register – SPDR ...

Page 169

... SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega128 Trailing edge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 ...

Page 170

... Double Speed Asynchronous Communication Mode Dual USART The ATmega128 has two USART’s, USART0 and USART1. The functionality for both USART’s is described below. USART0 and USART1 have different I/O registers as shown in Summary” on page neither is the UBRR0H or UCRS0C Registers. This means that in ATmega103 compatibility mode, the ATmega128 supports asynchronous operation of USART0 only ...

Page 171

... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA Refer to Figure 1 on page 2, Table 36 on page placement. ATmega128 Clock Generator OSC SYNC LOGIC PIN XCK CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN TxD ...

Page 172

... The XCK pin is only active when using Synchronous mode. Figure 80 Figure 80. Clock Generation Logic, Block Diagram Signal description: ATmega128 172 shows a block diagram of the clock generation logic. UBRR fosc ...

Page 173

... Equation for Calculating Baud Rate BAUD BAUD BAUD 1. The baud rate is defined to be the transfer rate in bit per second (bps). System Oscillator clock frequency ATmega128 Figure 80. Equation for Calculating (1) UBRR Value f f ...

Page 174

... The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As ing XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge. ATmega128 174 Figure 80 for details. ...

Page 175

... No transfers on the communication line (RxD or TxD). An IDLE line must be high. ⊕ … even n 1 – ⊕ … odd n 1 – Parity bit using even parity Parity bit using odd parity Data bit n of the character ATmega128 FRAME [5] [6] [7] [8] [P] Sp1 [Sp2] ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ...

Page 176

... UBRRL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSRB = (1<<RXEN)|(1<<TXEN); /* Set frame format: 8data, 2stop bit */ UCSRC = (1<<USBS)|(3<<UCSZ0); } Note: ATmega128 176 (1) UBRRH, r17 UBRRL, r16 r16, (1<<RXEN)|(1<<TXEN) UCSRB,r16 r16, (1<<USBS)|(3<<UCSZ0) ...

Page 177

... UCSRA,UDRE rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDR,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<<UDRE Put data into buffer, sends the data */ UDR = data; 1. See “About Code Examples” on page 8.. ATmega128 177 ...

Page 178

... UCSRA Register. When the Data Register empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDRE is set (provided that global interrupts are enabled). UDRE is cleared by writing UDR. When interrupt-driven data ATmega128 178 (1) UCSRB,TXB8 ...

Page 179

... Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDR I/O location. 2467V–AVR–02/11 ATmega128 179 ...

Page 180

... ATmega128 180 The following code example shows a simple USART receive function based on polling of the Receive Complete (RXC) flag. When using frames with less than eight bits the most significant bits of the data read from the UDR will be masked to zero. The USART has to be initialized before the function can be used ...

Page 181

... Get status and 9th bit, then data */ /* from buffer */ status = UCSRA; resh = UCSRB; resl = UDR error, return - status & (1<<FE)|(1<<DOR)|(1<<UPE) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); ATmega128 181 ...

Page 182

... If parity check is not enabled the UPE bit will always be read zero. For compati- bility with future devices, always set this bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 175 ATmega128 182 1. See “About Code Examples” on page The receive function example reads all the I/O registers into the register file before any compu- tation is done ...

Page 183

... The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. ATmega128 8. 183 ...

Page 184

... Including the first stop bit. Note that the receiver only uses the first stop bit of a frame. stop bit and the earliest possible beginning of the start bit of the next frame. ATmega128 184 IDLE ...

Page 185

... D S ⋅ – for Double Speed mode the ratio of the fastest incoming data rate that can be accepted in relation to fast and Table 76 list the maximum receiver baud rate error that can be tolerated. Note that ATmega128 STOP 1 (A) ( 0/1 0/1 0 0/1 ( ...

Page 186

... When the frame type bit (the first stop or the 9th bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. ATmega128 186 D ...

Page 187

... Do not use read-modify-write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC flag and this might accidentally be cleared when using SBI or CBI instructions. 2467V–AVR–02/11 ATmega128 187 ...

Page 188

... The UDREn flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn flag can generate a Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error ATmega128 188 ...

Page 189

... RxDn pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FEn, DORn and UPEn flags. • Bit 3 – TXENn: Transmitter Enable 2467V–AVR–02/11 “Multi-processor Communication Mode” on page RXCIEn TXCIEn UDRIEn RXENn TXENn R/W R/W R/W R ATmega128 186 UCSZn2 RXB8n TXB8n UCSRnB R/W R 189 ...

Page 190

... The Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting mismatch is detected, the UPEn flag in UCSRnA will be set. Table 78. UPMn Bits Settings UPMn1 ATmega128 190 – ...

Page 191

... Rising XCKn Edge Falling XCKn Edge – – – – UBRRn[7: R/W R/W R/W R ATmega128 Stop Bit(s) 1-bit 2-bits Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit Received Data Sampled (Input on RxDn Pin) Falling XCKn Edge Rising XCKn Edge UBRRn[11:8] 3 ...

Page 192

... UBRRnL contains the eight least significant bits of the USARTn baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler. ATmega128 192 2467V–AVR–02/11 ...

Page 193

... ATmega128 Table “Asynchronous Operational ⎞ Closest Match • – 100% ⎠ BaudRate f = 2.0000MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 95 0.0% 51 0.2% 47 ...

Page 194

... Max 230.4Kbps 460.8Kbps 1. UBRR = 0, Error = 0.0% ATmega128 194 f = 4.0000MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0.0% 16 2. ...

Page 195

... ATmega128 MHz f = 14.7456MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0. ...

Page 196

... Max 1. UBRR = 0, Error = 0.0% ATmega128 196 f = 16.0000MHz osc Error -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% 1Mbps U2X = 1 UBRR Error 832 0.0% 416 -0 ...

Page 197

... The device that initiates and terminates a transmission. The master also generates the SCL clock The device addressed by a master The device placing data on the bus The device reading data from the bus Figure 86, both bus lines are connected to the positive supply voltage through ATmega128 V CC ........ Device ...

Page 198

... START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. Figure 88. START, REPEATED START and STOP Conditions SDA SCL ATmega128 198 “Two-wire Serial Interface Characteristics” on page SDA SCL Data Stable ...

Page 199

... NACK after the final byte. The MSB of the data byte is transmitted first. 2467V–AVR–02/11 Addr MSB 1 2 START ATmega128 Addr LSB R/W ACK ...

Page 200

... Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration process. ATmega128 200 Data MSB 1 2 SLA+R/W shows a typical data transmission ...

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