ATMEGA128-16AI Atmel, ATMEGA128-16AI Datasheet - Page 251

• Manufacturer Part Number: ATMEGA128-16AI
• Description: IC AVR MCU 128K 16MHZ 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q1167170A

On-chip Debug
Related Register in
I/O Memory
On-chip Debug
Register – OCDR
Using the JTAG
Programming
Capabilities
Bibliography
2467V–AVR–02/11
The OCDR Register provides a communication channel from the running program in the micro-
controller to the debugger. The CPU can transfer a byte to the debugger by writing to this
location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate
to the debugger that the register has been written. When the CPU reads the OCDR Register the
7LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the
IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR
Register can only be accessed if the OCDEN fuse is programmed, and the debugger enables
access to the OCDR Register. In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
Programming of Atmel
TMS, TDI, and TDO. These are the only pins that need to be controlled/observed to perform
JTAG programming (in addition to power pins). It is not required to apply 12V externally. The
JTAGEN fuse must be programmed and the JTD bit in the MCUCSR Register must be cleared
to enable the JTAG Test Access Port.
The JTAG programming capability supports:
•
•
•
•
The Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 are
programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a
security feature that ensures no back-door exists for reading out the content of a secured
device.
The details on programming through the JTAG interface and programming specific JTAG
instructions are given in the section
For more information about general Boundary-scan, the following literature can be consulted:
•
•
Bit
Read/Write
Initial Value
Flash programming and verifying
EEPROM programming and verifying
Fuse programming and verifying
Lock bit programming and verifying
IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan
Architecture, IEEE, 1993
Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley,
1992
MSB/IDRD
R/W
7
0
®
AVR
R/W
6
0
®
devices via JTAG is performed via the four-pin JTAG port, TCK,
R/W
5
0
“Programming Via the JTAG Interface” on page
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
ATmega128
LSB
R/W
0
0
OCDR
305.
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