ATMEGA128-16AI Atmel, ATMEGA128-16AI Datasheet - Page 141

• Manufacturer Part Number: ATMEGA128-16AI
• Description: IC AVR MCU 128K 16MHZ 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q1167170A

Extended
Timer/Counter
Interrupt Flag Register
– ETIFR
2467V–AVR–02/11
TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is executed.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
• Bit 7:6 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be set to zero when ETIFR is written.
• Bit 5 – ICF3: Timer/Counter3, Input Capture Flag
This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register
(ICR3) is set by the WGM3:0 to be used as the TOP value, the ICF3 flag is set when the counter
reaches the TOP value.
ICF3 is automatically cleared when the Input Capture 3 interrupt vector is executed. Alterna-
tively, ICF3 can be cleared by writing a logic one to its bit location.
• Bit 4 – OCF3A: Timer/Counter3, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output
Compare Register A (OCR3A).
Note that a forced output compare (FOC3A) strobe will not set the OCF3A flag.
OCF3A is automatically cleared when the Output Compare Match 3 A interrupt vector is exe-
cuted. Alternatively, OCF3A can be cleared by writing a logic one to its bit location.
• Bit 3 – OCF3B: Timer/Counter3, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output
Compare Register B (OCR3B).
Note that a forced output compare (FOC3B) strobe will not set the OCF3B flag.
OCF3B is automatically cleared when the Output Compare Match 3 B interrupt vector is exe-
cuted. Alternatively, OCF3B can be cleared by writing a logic one to its bit location.
• Bit 2 – TOV3: Timer/Counter3, Overflow Flag
The setting of this flag is dependent of the WGM3:0 bits setting. In normal and CTC modes, the
TOV3 flag is set when the timer overflows. Refer to
behavior when using another WGM3:0 bit setting.
TOV3 is automatically cleared when the Timer/Counter3 Overflow interrupt vector is executed.
Alternatively, TOV3 can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF3C: Timer/Counter3, Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output
Compare Register C (OCR3C).
Note that a forced output compare (FOC3C) strobe will not set the OCF3C flag.
OCF3C is automatically cleared when the Output Compare Match 3 C interrupt vector is exe-
cuted. Alternatively, OCF3C can be cleared by writing a logic one to its bit location.
• Bit 0 – OCF1C: Timer/Counter1, Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register C (OCR1C).
Bit
Read/Write
Initial Value
R/W
7
–
0
R/W
6
–
0
ICF3
R/W
5
0
OCF3A
R/W
4
0
OCF3B
R/W
3
0
Table 52 on page 104
TOV3
R/W
2
0
OCF3C
R/W
1
0
OCF1C
R/W
ATmega128
0
0
for the TOV3 flag
ETIFR
141