ATMEGA128-16AI Atmel, ATMEGA128-16AI Datasheet - Page 36

IC AVR MCU 128K 16MHZ 64-TQFP

ATMEGA128-16AI

Manufacturer Part Number
ATMEGA128-16AI
Description
IC AVR MCU 128K 16MHZ 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128-16AI

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Q1167170A

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Asynchronous Timer
Clock – clk
ADC Clock – clk
XTAL Divide Control
Register – XDIV
Clock Sources
36
ATmega128
ASY
ADC
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Coun-
ter as a real-time counter even when the device is in sleep mode.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The XTAL Divide Control Register is used to divide the Source clock frequency by a number in
the range 2 - 129. This feature can be used to decrease power consumption when the require-
ment for processing power is low.
• Bit 7 – XDIVEN: XTAL Divide Enable
When the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals (clk
clk
can be written run-time to vary the clock frequency as suitable to the application.
• Bits 6..0 – XDIV6..XDIV0: XTAL Divide Select Bits 6 - 0
These bits define the division factor that applies when the XDIVEN bit is set (one). If the value of
these bits is denoted d, the following formula defines the resulting CPU and peripherals clock
frequency f
The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is written to
one, the value written simultaneously into XDIV6..XDIV0 is taken as the division factor. When
XDIVEN is written to zero, the value written simultaneously into XDIV6..XDIV0 is rejected. As
the divider divides the master clock input to the MCU, the speed of all peripherals is reduced
when a division factor is used.
When the system clock is divided, Timer/Counter0 can be used with Asynchronous clock only. The fre-
quency of the asynchronous clock must be lower than 1/4th of the frequency of the scaled down Source
clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter0 registers may fail.
The device has the following clock source options, selectable by Flash fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 6. Device Clocking Options Select
Bit
Read/Write
Initial Value
Device Clocking Option
External Crystal/Ceramic Resonator
External Low-frequency Crystal
External RC Oscillator
Calibrated Internal RC Oscillator
External Clock
ADC
, clk
CPU
CLK
, clk
XDIVEN
:
R/W
7
0
FLASH
) is divided by the factor defined by the setting of XDIV6 - XDIV0. This bit
XDIV6
R/W
6
0
XDIV5
R/W
5
0
f
CLK
XDIV4
R/W
4
0
=
Source clock
--------------------------------- -
XDIV3
129 d
R/W
3
0
XDIV2
R/W
2
0
XDIV1
R/W
1
0
CKSEL3..0
1111 - 1010
1000 - 0101
0100 - 0001
XDIV0
R/W
1001
0000
0
0
(1)
XDIV
2467V–AVR–02/11
I/O
,

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