ATMEGA128-16AI Atmel, ATMEGA128-16AI Datasheet - Page 113

• Manufacturer Part Number: ATMEGA128-16AI
• Description: IC AVR MCU 128K 16MHZ 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q1167170A

Definitions
Compatibility
2467V–AVR–02/11
See “Output Compare Units” on page
match flag (OCFnA/B/C) which can be used to generate an output compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-
gered) event on either the Input Capture Pin (ICPn) or on the Analog Comparator pins
“Analog Comparator” on page
Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined
by either the OCRnA Register, the ICRn Register, or by a set of fixed values. When using
OCRnA as TOP value in a PWM mode, the OCRnA Register can not be used for generating a
PWM output. However, the TOP value will in this case be double buffered allowing the TOP
value to be changed in run time. If a fixed TOP value is required, the ICRn Register can be used
as an alternative, freeing the OCRnA to be used as PWM output.
The following definitions are used extensively throughout the document:
Table 57. Definitions
The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit
AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version
regarding:
•
•
•
The following control bits have changed name, but have same functionality and register location:
•
•
•
The following registers are added to the 16-bit Timer/Counter:
•
•
The following bits are added to the 16-bit Timer/Counter Control Registers:
•
•
•
Interrupt flag and mask bits for output compare unit C are added.
The 16-bit Timer/Counter has improvements that will affect the compatibility in some special
cases.
BOTTOM
MAX
TOP
All 16-bit Timer/Counter related I/O register address locations, including timer interrupt
registers.
Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers.
Interrupt vectors.
PWMn0 is changed to WGMn0.
PWMn1 is changed to WGMn1.
CTCn is changed to WGMn2.
Timer/Counter Control Register C (TCCRnC).
Output Compare Register C, OCRnCH and OCRnCL, combined OCRnC.
COM1C1:0 are added to TCCR1A.
FOCnA, FOCnB, and FOCnC are added in the new TCCRnC Register.
WGMn3 is added to TCCRnB.
The counter reaches the BOTTOM when it becomes 0x0000.
The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be one of the fixed values:
0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCRnA or ICRn
Register. The assignment is dependent of the mode of operation.
227.) The Input Capture unit includes a digital filtering unit (Noise
120.. The compare match event will also set the compare
ATmega128
(See
113