UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 878
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UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
19.16 Communication Operations
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
The following shows three operation procedures together with flowcharts.
(1) Master operation in single master system
(2) Master operation in multimaster system
(3) Slave operation
The flowchart when using the V850ES/JG3-U and V850ES/JH3-U as the master in a single master system is
shown below.
This flowchart is broadly divided into initial settings and communication processing. Execute the initial settings at
startup. If communication with a slave is required, prepare the communication and then execute communication
processing.
In the I
specifications when the bus takes part in a communication. Here, when data and the clock are at a high level for a
certain period (1 frame), the V850ES/JG3-U or V850ES/JH3-U takes part in communication in a bus release state.
This flowchart is broadly divided into initial settings, communication waiting, and communication processing. The
processing when the V850ES/JG3-U or V850ES/JH3-U loses in arbitration and is specified as the slave is omitted
here, and only the processing as the master is shown. Execute the initial settings at startup to take part in
communication. Then, wait for the communication request as the master or wait for the specification as the slave.
The actual communication is performed in the communication processing, and includes arbitration with other
masters data as well as transmission/reception with the slave.
An example of when the V850ES/JG3-U or V850ES/JH3-U is used as the slave of the I
When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait for
INTIICn interrupt occurrence (communication waiting). When the INTIICn interrupt occurs, the communication
status is judged and its result is passed as a flag to the main processing.
By checking the flags, the necessary communication processing can be performed.
Remark
2
C0n bus multimaster system, whether the bus is released or used cannot be judged by the I
n = 0 to 2
2
CHAPTER 19 I
C0n bus is shown below.
Page 878 of 1408
2
C BUS
2
C bus
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