UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 175
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UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 175 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
5.2
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
The pins used to connect an external device are listed in the table below.
AD0 to AD15
A16 to A23
WAIT
CLKOUT
WR0, WR1
RD
ASTB
HLDRQ
HLDAK
CS0, CS2, CS3
AD0 to AD15
A0 to A15
A16 to A21
WAIT
CLKOUT
WR0, WR1
RD
HLDRQ
HLDAK
CS0, CS2, CS3
AD0 to AD15
WAIT
CLKOUT
WR0, WR1
RD
ASTB
CS0, CS2, CS3
Bus Control Pins
Bus Control Pin
Bus Control Pin
Bus Control Pin
Table 5-1. V850ES/JH3-U Bus Control Pins (Multiplexed Bus)
Table 5-3. V850ES/JG3-U Bus Control Pins (Multiplexed Bus)
Table 5-2. V850ES/JH3-U Bus Control Pins (Separate Bus)
PDL0 to PDL15
PDH0 to PDH5
PCM0
PCM1
PCT0, PCT1
PCT4
PCT6
PCM3
PCM2
PCS0, PCS2, PCS3
PDL0 to PDL15
P90 to P915
PDH0 to PDH5
PCM0
PCM1
PCT0, PCT1
PCT4
PCM3
PCM2
PCS0, PCS2, PCS3
PDL0 to PDL15
PCM0
PCM1
PCT0, PCT1
P61
P62
P63, P64, P65
Alternate-Function Pin
Alternate-Function Pin
Alternate-Function Pin
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
Address/data bus
Address bus
External wait control
Internal system clock
Write strobe signal
Read strobe signal
Address strobe signal
Bus hold control
Chip select
Data bus
Address bus
Address bus
External wait control
Internal system clock
Write strobe signal
Read strobe signal
Bus hold control
Chip select
Address/data bus
External wait control
Internal system clock
Write strobe signal
Read strobe signal
Address strobe signal
Chip select
CHAPTER 5 BUS CONTROL FUNCTION
Function
Function
Function
Page 175 of 1408
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