UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 1158
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UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
22.6 Transfer Types
write cycle, the transfer destination address is output and writing is performed from the DMAC to the destination.
between the transfer source and destination for DMA transfer of two cycles, the operation is performed as follows.
same transfer size as the register size. For example, for DMA transfer to an 8-bit register, be sure to specify byte (8-bit)
transfer.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
As a transfer type, the 2-cycle transfer is supported.
In two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle.
In the read cycle, the transfer source address is output and reading is performed from the source to the DMAC. In the
An idle cycle of one clock is always inserted between a read cycle and a write cycle. If the data bus width differs
<16-bit data transfer>
For DMA transfer executed to an on-chip peripheral I/O register (transfer source/destination), be sure to specify the
Remark
<1> Transfer from 32-bit bus → 16-bit bus
<2> Transfer from 16-/32-bit bus to 8-bit bus
<3> Transfer from 8-bit bus to 16-/32-bit bus
<4> Transfer between 16-bit bus and 32-bit bus
A read cycle (the higher 16 bits are in a high-impedance state) is generated, followed by generation of a write
cycle (16 bits).
A 16-bit read cycle is generated once, and then an 8-bit write cycle is generated twice.
An 8-bit read cycle is generated twice, and then a 16-bit write cycle is generated once.
A 16-bit read cycle is generated once, and then a 16-bit write cycle is generated once.
The bus width of each transfer target (transfer source/destination) is as follows.
• On-chip peripheral I/O: 16-bit bus width
• Internal RAM:
• External memory:
32-bit bus width
8-bit or 16-bit bus width
CHAPTER 22 DMA FUNCTION (DMA CONTROLLER)
Page 1158 of 1408
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