UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 420
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 420 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(i) Operation to write 0 (without conflict with setting)
(ii) Operation to write 0 (conflict with setting)
(e) Clearing overflow flag
(TABnOVF bit)
(TABnOVF bit)
Overflow flag
Overflow flag
The overflow flag can be cleared to 0 by clearing the TABnOVF bit to 0 with the CLR instruction and by writing
8-bit data (bit 0 is 0) to the TABnOPT0 register. To accurately detect an overflow, read the TABnOVF bit when it
is 1, and then clear the overflow flag by using a bit manipulation instruction.
Remark
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set overflow information may
be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred
even when an overflow actually has occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to
0 with the CLR instruction, the overflow flag remains set even after execution of the CLR instruction.
0 write signal
0 write signal
set signal
set signal
Overflow
Overflow
n = 0, 1
L
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(iii) Operation to clear to 0 (without conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
(TABnOVF bit)
(TABnOVF bit)
access signal
access signal
Overflow flag
Overflow flag
0 write signal
0 write signal
set signal
set signal
Overflow
Overflow
Register
Register
L
H
Read
Read
Write
Write
Page 420 of 1408
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