UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 1005
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 1005 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(5) UF0 EP3 status register L (UF0E3SL)
UF0E3SL
Bit position
This register stores the value that is to be returned in response to the GET_STATUS Endpoint3 request.
This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when
the EP0NKA bit is set to 1.
If an error occurs in Endpoint3, the E3HALT bit is set to 1. A write access to this register is ignored while a USB-
side access to Endpoint3 is being received.
The hardware automatically transmits the contents of this register to the host when it has received the
GET_STATUS Endpoint3 request. If Endpoint3 has stalled, the UF0BI2 register is cleared and the BKI2NK bit is
cleared to 0.
Because writing this register is always masked when transfer to Endpoint3, rather than control transfer, is executed,
be sure to check this register to see if data has been correctly written to it.
Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite
0
7
0
the register contents after confirming that the bit has been set, in order to prevent conflict
between a read access and a write access.
E3HALT
Bit name
6
0
This bit indicates the status of Endpoint3.
This bit is set to 1 by hardware when the SET_FEATURE Endpoint3 request has been
received. It is cleared to 0 by hardware when the CLEAR_FEATURE Endpoint3 request,
SET_CONFIGURATION request, or the SET_INTERFACE request for the Interface to
which Endpoint3 is linked has correctly been received. DATA PID is initialized to DATA0.
5
0
1: Stalled
0: Not stalled
4
0
3
0
CHAPTER 20 USB FUNCTION CONTROLLER (USBF)
2
0
Function
1
0
E3HALT
0
00200158H
Address
Page 1005 of 1408
After reset
00H
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