UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 300
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UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
7.5.7
is set to 1. Each time the valid edge input to the TIAAnm pin has been detected, the count value of the 16-bit counter is
stored in the TAAnCCRm register, and the 16-bit counter is cleared to 0000H.
signal (INTTAAnCCm) occurs.
by using the TAAnIOC1 register.
clock is fixed to the TIAAn0 pin. At this time, clear the TAAnIOC1.TAAnIS1 and TAAnIOC1.TAAnIS0 bits to 00 (capture
trigger input (TIAAn0 pin): No edge detection).
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
In the pulse width measurement mode, 16-bit timer/event counter AA starts counting when the TAAnCTL0.TAAnCE bit
The interval of the valid edge can be measured by reading the TAAnCCRm register after a capture interrupt request
Select either the TIAAn0 or TIAAn1 pin as the capture trigger input pin. Specify “No edge detection” for the unused pins
When an external clock is used as the count clock, measure the pulse width of the TIAAn1 pin because the external
Pulse width measurement mode (TAAnMD2 to TAAnMD0 bits = 110)
trigger input)
trigger input)
TIAAn0 pin
TIAAn1 pin
Remark
(capture
(capture
n = 0 to 3, 5
m = 0, 1
detector
detector
Figure 7-39. Configuration in Pulse Width Measurement Mode
Edge
Edge
selection
TAAnCE bit
Count
clock
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
TAAnCCR0 register
(capture)
TAAnCCR1 register
Clear
16-bit counter
(capture)
INTTAAnOV
INTTAAnCC0
INTTAAnCC1
signal
Page 300 of 1408
signal
signal
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