UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 337
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 337 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(5) TABn I/O control register 2 (TABnIOC2)
The TABnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal
(TIAB00/EVTAB1 pin) and external trigger input signal (TIAB00/TRGAB1 pin).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TABnIOC2
(n = 0, 1)
After reset: 00H
TABnEES1
Cautions 1. Rewrite the TABnEES1, TABnEES0, TABnETS1, and
TABnETS1
0
0
1
1
0
0
1
1
0
7
TABnEES0
TABnETS0
R/W
2. The TABnEES1 and TABnEES0 bits are valid only when
3. The TABnETS1 and TABnETS0 bits are valid only when
0
1
0
1
0
1
0
1
6
0
TABnETS0 bits when the TABnCTL0.TABnCE bit = 0. (The
same value can be written when the TABnCE bit = 1.) If
rewriting was mistakenly performed, clear the TABnCE bit
to 0 and then set the bits again.
the TABnCTL1.TABnEEE bit = 1 or when the external
event
TABnCTL1.TABnMD0 bits = 001) has been set.
the
(TABnCTL1.TABnMD2 to TABnCTL1.TABnMD0 bits = 010)
or the one-shot pulse output mode (TABnCTL1.TABnMD2
to TABnCTL1.TABnMD0 = 011) is set.
Address:
External trigger input signal (TIAB00/TRGAB1 pin) valid edge setting
External event count input signal (TIAB00/EVTAB1 pin) valid edge setting
No edge detection (external event count invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (external trigger invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
external
5
0
count
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
TAB0IOC2 FFFFF544H, TAB1IOC2 FFFFF564H
4
0
mode
trigger
TABnEES1 TABnEES0 TABnETS1 TABnETS0
3
(TABnCTL1.TABnMD2
pulse
2
output
1
mode
0
to
Page 337 of 1408
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