UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 437
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 437 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
9.4
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(1) TMT0 control register 0 (TT0CTL0)
Registers
The TT0CTL0 register is an 8-bit register that controls the operation of TMT0.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The same value can always be written to the TT0CTL0 register by software.
TT0CTL0
After reset: 00H
Note The TT0OPT0.TT0OVF bit and 16-bit counter are reset simultaneously.
Cautions 1. Set the TT0CKS2 to TT0CKS0 bits when the TT0CE bit = 0.
Remark
TT0CKS2
TT0CE
TT0CE
<7>
0
1
0
0
0
0
1
1
1
1
Moreover, timer outputs (TOT00 and TOT01) are reset at the same time as the
16-bit counter.
TMT0 operation disabled (TMT0 reset asynchronously
TMT0 operation enabled. TMT0 operation start
TT0CKS1
R/W
f
2. Be sure to set bits 3 to 6 to “0”.
XX
: Peripheral clock
6
0
0
0
1
1
0
0
1
1
When the value of the TT0CE bit is changed from 0 to 1, the TT0CKS2
to TT0CKS0 bits can be set simultaneously.
Address: FFFF600H
TT0CKS0
5
0
0
1
0
1
0
1
0
1
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
f
f
f
f
f
f
f
f
XX
XX
XX
XX
XX
XX
XX
XX
/2
/4
/8
/16
/32
/64
/128
4
0
TMT0 operation control
Internal count clock selection
3
0
TT0CKS2 TT0CKS1 TT0CKS0
2
Note
)
1
0
Page 437 of 1408
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