UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 1157
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UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
22.4 Transfer Targets
22.5 Transfer Modes
request, transfer is performed again once. This operation continues until a terminal count occurs.
request always takes precedence.
generated in a transfer cycle, DMA transfer of the channel with the lower priority is executed after the bus is released to the
CPU (the new transfer request of the same channel is ignored in the transfer cycle).
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Table 22-2 shows the relationship between the transfer targets (√: Transfer enabled, ×: Transfer disabled).
Caution The operation is not guaranteed for combinations of transfer destination and source marked with “×”
Single transfer is supported as the transfer mode.
In single transfer mode, the bus is released at each byte/halfword transfer. If there is a subsequent DMA transfer
When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA
If a new transfer request of the same channel and a transfer request of another channel with a lower priority are
in Table 22-2.
On-chip
Internal RAM
External memory
Internal ROM
peripheral I/O
Table 22-2. Relationship Between Transfer Targets
Internal ROM
×
×
×
×
CHAPTER 22 DMA FUNCTION (DMA CONTROLLER)
Peripheral I/O
On-Chip
√
√
√
×
Transfer Destination
Internal RAM
√
×
√
×
External Memory
√
√
√
×
Page 1157 of 1408
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