UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 758
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UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Remark f
Baud Rate
1,000,000
1,250,000
2,000,000
2,500,000
3,000,000
To set the baud rate, perform the following calculation for setting the UCnCTL1 and UCnCTL2 registers (when
using internal clock).
<1> Set k to fxx/2/(2 × target baud rate) and m to 0.
<2> If k is 256 or greater (k ≥ 256), reduce k to half (k/2) and increment m by 1 (m + 1).
<3> Repeat Step <2> until k becomes less than 256 (k < 256).
<4> Round off the first decimal point of k to the nearest whole number.
<5> Set the value of m to UCnCTL1 register and the value of k to the UCnCTL2 register.
Example: When f
The representative examples of baud rate settings are shown below.
(bps)
153,600
312,500
625,000
19,200
31,250
38,400
76,800
1,200
2,400
4,800
9,600
If k becomes 256 after round-off, perform Step <2> again to set k to 128.
300
600
ERR: Baud rate error (%)
XX
:
UCnCTL1 UCnCTL2
<1> k = 480,000,000/2/(2 × 153,600) = 78.125…, m = 0
<2>, <3> k = 78.125… < 256, m = 0
<4> Set value of UCnCTL2 register: k = 78 = 4EH, set value of UCnCTL1 register: m = 0
Actual baud rate = 48,000,000/2/(2 × 78)
Baud rate error = {48,000,000/2/(2 × 78 × 153,600) − 1} × 100
Main clock frequency
08H
07H
06H
05H
04H
03H
02H
01H
01H
00H
00H
00H
00H
00H
00H
00H
00H
00H
XX
f
XX
= 48 MHz and target baud rate = 153,600 bps
= 48 MHz
9CH
9CH
9CH
9CH
9CH
9CH
9CH
C0H
9CH
9CH
0CH
4EH
0AH
26H
13H
06H
05H
04H
= 153,846 [bps]
= 0.160 [%]
Table 17-4. Baud Rate Generator Setting Data
ERR (%)
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
−4.00 Setting prohibited
−4.00
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.00
0.16
0.16
0.16
1.05
1.05
0.00
0.00
0.00
UCnCTL1 UCnCTL2
Setting prohibited
07H
06H
05H
04H
03H
02H
01H
01H
00H
00H
00H
00H
00H
00H
00H
f
XX
= 32 MHz
D0H
D0H
D0H
D0H
D0H
D0H
D0H
D0H
0DH
1AH
80H
68H
34H
08H
04H
ERR (%)
−1.54
−1.54
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.00
0.16
0.16
0.16
0.00
0.00
UCnCTL1 UCnCTL2
Setting prohibited
07H
06H
05H
04H
03H
02H
01H
00H
00H
00H
00H
00H
00H
00H
00H
f
XX
= 24 MHz
9CH
9CH
9CH
9CH
9CH
9CH
9CH
C0H
9CH
4EH
0AH
27H
13H
06H
05H
Page 758 of 1408
ERR (%)
−4.00
−4.00
−2.3
0.16
0.16
0.16
0.16
0.16
0.16
0.00
0.16
0.16
0.16
1.05
0.00
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