UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 599
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 599 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
<1> 100% output is selected by the valley interrupt (with a match with the 16-bit counter).
<2> 100% output is canceled by the valley interrupt (without a match with the 16-bit counter).
<3> 100% output is selected by the crest interrupt (without a match with the 16-bit counter).
<4> 100% output is canceled by the crest interrupt (without a match with the 16-bit counter).
Remarks 1.
The valley interrupt forcibly lowers the timer output, but raising the timer output takes precedence when
the value of the TAB1CCRm register matches the value of the 16-bit counter. As a result, the 100% output
is produced.
The valley interrupt forcibly lowers the timer output. This cancels the 100% output.
The crest interrupt forcibly raises the timer output. This produces the 100% output.
The crest interrupt forcibly raises the timer output. This cancels the 100% output.
of timer output
buffer register
Forced timing
TAB1CCR1
TAB1CCR0
2. m = 1 to 3
TOAB1T1
TOAB1B1
pin output
pin output
register
register
counter
CCR1
16-bit
means forcible raising and means forcible lowering.
0000H
Figure 11-10. 100% PWM Output Waveform (With Dead Time)
i
i
i
i
<1>
0000H
0000H
output
100%
<2>
i
M
CHAPTER 11 MOTOR CONTROL FUNCTION
i
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i
i
<3>
0000H
0000H
output
100%
<4>
i
i
i
Page 599 of 1408
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