UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 825
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UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 825 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Note
Remark
Condition for clearing (SPIEn bit = 0)
• Cleared by instruction
• After reset
During address transfer, an interrupt occurs at the falling edge of the ninth clock regardless of this bit setting. This
bit setting becomes valid when the address transfer is completed. In master mode, a wait state is inserted at the
falling edge of the ninth clock during address transfer. For a slave device that has received a local address, a wait
state is inserted at the falling edge of the ninth clock after ACK is generated. The slave device that has received
an extension code, however, enters a wait state at the falling edge of the eighth clock.
Condition for clearing (WTIMn bit = 0)
• Cleared by instruction
• After reset
The ACKEn bit setting is invalid for address reception by the slave device. In this case, ACK is generated when
the addresses match.
However, the ACKEn bit setting is valid for reception of the extension code. Set the ACKEn bit in the system that
receives the extension code.
Condition for clearing (ACKEn bit = 0)
• Cleared by instruction
• After reset
WTIMn
ACKEn
SPIEn
0
1
0
1
0
1
This flag’s signal is invalid when the IICEn bit = 0.
Note
Note
Note
n = 0 to 2
Disabled
Enabled
Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and the wait state is set.
Slave mode: After input of eight clocks, the clock is set to low level and the wait state is set for the
Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and the wait state is set.
Slave mode: After input of nine clocks, the clock is set to low level and the wait state is set for the
Acknowledgment disabled.
Acknowledgment enabled. During the ninth clock period, the SDA0n line is set to low level.
Enabling/disabling generation of interrupt request when stop condition is detected
master device.
master device.
Control of wait state and interrupt request generation
Acknowledgment control
Condition for setting (SPIEn bit = 1)
• Set by instruction
Condition for setting (WTIMn bit = 1)
• Set by instruction
Condition for setting (ACKEn bit = 1)
• Set by instruction
CHAPTER 19 I
Page 825 of 1408
2
C BUS
(2/4)
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