UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 783

• Manufacturer Part Number: UPD70F3769GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-U 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3769GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
SIFn pin capture
INTCFnR signal
(2) Operation timing
CFnTSF bit
SCKFn pin
SOFn pin
SIFn pin
(1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E1H to the CFnCTL0 register, and select the transmission/reception mode and MSB first at the
(4) Set the CFnSTR.CFnTSF bit to 1 by writing the transmit data to the CFnTX register, and start
(5) When transmission/reception is started, output the serial clock to the SCKFn pin, output the transmit
(6) When transmission/reception of the transfer data length set by the CFnCTL2 register is completed,
(7) Read the CFnRX register.
(8) To continue transmission/reception, write the transmit data to the CFnTX register again.
(9) Read the CFnRX register.
(10) To end transmission/reception, write CFnCTL0.CFnPWR bit = 0, CFnCTL0.CFnTXE bit = 0, and
Remark
timing
f
same time as enabling the operation of the communication clock (f
transmission/reception.
data to the SOFn pin in synchronization with the serial clock, and capture the receive data of the SIFn
pin.
stop the serial clock output, transmit data output, and data capturing, generate the reception
completion interrupt request signal (INTCFnR) at the last edge of the serial clock, and clear the
CFnTSF bit to 0.
CFnCTL0.CFnRXE bit = 0.
XX
/2 or f
(1)
(2)
(3)
n = 0 to 4
(4)
XX
/3, and master mode.
(5)
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4 Bit 3 Bit 2
Bit 4 Bit 3 Bit 2
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
Bit 1
Bit 1
(6)
(7)
Bit 0
Bit 0
(8)
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
CCLK
Bit 4
Bit 4
).
Bit 3 Bit 2
Bit 3 Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
(9)
(10)
Page 783 of 1408
CCLK
) =