UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 1402
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 1402 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
LD.H
LDSR
LD.HU
LD.W
MOV
MOVEA
MOVHI
MUL
MULH
MULHI
MULU
NOP
NOT
NOT1
Mnemonic
disp16[reg1],reg2
reg2,regID
disp16[reg1],reg2
disp16[reg1],reg2
reg1,reg2
imm5,reg2
imm32,reg1
imm16,reg1,reg2
imm16,reg1,reg2
reg1,reg2,reg3
imm9,reg2,reg3
reg1,reg2
imm5,reg2
imm16,reg1,reg2
reg1,reg2,reg3
imm9,reg2,reg3
reg1,reg2
bit#3,disp16[reg1]
reg2,[reg1]
Operand
rrrrr111001RRRRR
ddddddddddddddd0
rrrrr111111RRRRR
0000000000100000
r r rr r1 11 11 1 RRRRR
ddddddddddddddd1
r r rr r1 11 00 1 RRRRR
ddddddddddddddd1
r r rr r0 00 00 0 RRRRR GR[reg2]←GR[reg1]
r r r r r 0 1 0 0 0 0 i i i i i
00000110001RRRRR
i i i i i i i i i i i i i i i i
I I I I I I I I I I I I I I I I
r r rr r1 10 00 1 RRRRR
i i i i i i i i i i i i i i i i
r r rr r1 10 01 0 RRRRR
i i i i i i i i i i i i i i i i
r r rr r1 11 11 1 RRRRR
wwwww01000100000
r r r r r 1 1 1 1 1 1 i i i i i
wwwww01001IIII 00
r r rr r0 00 11 1 RRRRR GR[reg2]←GR[reg2]
r r r r r 0 1 0 1 1 1 i i i i i
r r rr r1 10 11 1 RRRRR
i i i i i i i i i i i i i i i i
r r rr r1 11 11 1 RRRRR
wwwww01000100010
r r r r r 1 1 1 1 1 1 i i i i i
wwwww01001IIII 10
0000000000000000 Pass at least one clock cycle doing nothing.
r r rr r0 00 00 1 RRRRR GR[reg2]←NOT(GR[reg1])
01bbb111110RRRRR
dddddddddddddddd
r r rr r1 11 11 1 RRRRR
0000000011100010
Opcode
Note 13
Note 13
Note 12
Note 8
Note 8
Note 8
adr←GR[reg1]+sign-extend(disp16)
GR[reg2]←sign-extend(Load-memory(adr,Halfword))
SR[regID]←GR[reg2]
adr←GR[reg1]+sign-extend(disp16)
GR[reg2]←zero-extend(Load-memory(adr,Halfword)
adr←GR[reg1]+sign-extend(disp16)
GR[reg2]←Load-memory(adr,Word)
GR[reg2]←sign-extend(imm5)
GR[reg1]←imm32
GR[reg2]←GR[reg1]+sign-extend(imm16)
GR[reg2]←GR[reg1]+(imm16 ll 0
GR[reg3] ll GR[reg2]←GR[reg2]xGR[reg1]
Note 14
GR[reg3] ll GR[reg2]←GR[reg2]xsign-extend(imm9)
GR[reg2]←GR[reg2]
GR[reg2]←GR[reg1]
GR[reg3] ll GR[reg2]←GR[reg2]xGR[reg1]
Note 14
GR[reg3] ll GR[reg2]←GR[reg2]xzero-extend(imm9)
adr←GR[reg1]+sign-extend(disp16)
Z flag←Not(Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,Z flag)
adr←GR[reg1]
Z flag←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,Z flag)
Note 6
Note 6
Note 6
Operation
xGR[reg1]
xsign-extend(imm5)
ximm16
Other than regID = PSW
regID = PSW
16
)
Note 6
APPENDIX D INSTRUCTION SET LIST
Note 3
Note 3
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
3
3
1
Execution
i
Clock
Note 3
Note 3
1
1
1
1
1
1
1
2
1
1
4
4
1
1
1
4
4
1
1
3
3
r
Note 3
Note 3
Note
Note
Note
11
11
11
1
1
1
1
2
1
1
5
5
2
2
2
5
5
1
1
3
3
l
CY OV S
×
Page 1402 of 1408
×
0
Flags
×
×
Z SAT
×
×
×
×
×
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