UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 1106
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 1106 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Bit position
8
7
6
5
4
3
2
1
0
SERR
Enable
Wait Cycle
Control
Parity Error
Response
VGA Pallet
Snoop
Memory
Write and
Invalidate
Special
Cycle
Bus Master
Memory
Space
I/O Space
Bit name
SERR Enable Bit
Set this bit to “1” when sending system errors via the SERR signal.
Wait Cycle Control Enable Bit
This bit is fixed to “0” because the USB host controller does not support address/data
stepping.
This bit is read-only.
Parity Error Response Enable Bit
Set this bit to “1” when checking parity errors.
VGA Palette Snoop Enable Bit
This bit is fixed to “0” because the USB host controller does not support VGA palette snoop.
This bit is read-only.
Memory Write and Invalidate Enable Bit
This bit is fixed to “0” because the USB host controller does not support Memory Write and
Invalidate.
This bit is read-only.
Special Cycle Enable Bit
This bit is fixed to “0” because the USB host controller does not support Special Cycle.
This bit is read-only.
Bus Master Enable Bit
Enables bus master accesses for the PCI bus and must be set to “1” before accessing
SRAM via the system bus. Set this bit to “1” upon host controller initialization.
Memory Space Access Enable Bit
Enables memory accesses according to the PCI Specification, and must be set to “1”
before accessing registers. Set this bit to “1” upon host controller initialization.
I/O Space Access Enable Bit
Enables I/O accesses defined in the PCI Specification, but this bit is fixed to “0” because
the USB host controller does not use I/O accesses.
This bit is read-only.
CHAPTER 21 USB HOST CONTROLLER (USBH)
Function
Page 1106 of 1408
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