UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 1159
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UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 1159 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
22.7 DMA Channel Priorities
22.8 Time Related to DMA Transfer
shown below.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
<1> DMA request response time
<2> Memory access
The DMA channel priorities are fixed as follows.
The priorities are checked for every transfer cycle.
The time required to respond to a DMA request, and the minimum number of clocks required for DMA transfer are
Notes 1. One clock is always inserted between a read cycle and a write cycle in DMA transfer.
DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3
Single transfer: DMA response time (<1>) + Transfer source memory access (<2>) + 1
2. If an external interrupt (INTPn) is specified as the trigger to start DMA transfer, noise elimination time is
3. Two clocks are required for a DMA cycle.
4. More wait cycles are necessary for accessing a specific peripheral I/O register (for details, see 3.4.9 (2)).
5. This is the number of clocks required when the following wait specifications have been made: 1 data wait (set
added (n = 00 to 18).
by the DWC0 register), 0 address waits (set by the AWC register), and 0 idle waits (set by the BCC register).
memory access (<2>)
DMA Cycle
External memory access
Internal RAM access
Peripheral I/O register access
USB register access
Data-only RAM access
4 clocks (MIN.) + Noise elimination time
Depends on connected memory.
2 clocks
3 clocks + Number of wait cycles specified by VSWC register
4 clocks
4 clocks
CHAPTER 22 DMA FUNCTION (DMA CONTROLLER)
Note 3
Note 5
Note 5
Minimum Number of Execution Clocks
Note 2
Note 1
+ Transfer destination
Page 1159 of 1408
Note 4
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